Dry Etching of
Deep Backside Vias in InP
Maria Huffman 1 ,
Timothy Engel 1 , Nicholas Pfister 1 , Gabriel Arevalo 1 , Tom Brown 1 ,
Maya Farhoud 1 , Ron
Miller 1 , Ben Keppeler 1 , John Staroba 1 , Richard Jefferies 2 .
1 Agilent
Technologies Inc.,
95403. Email: maria_huffman@agilent.com;
Phone:707-577-4895 2 Trikon Technologies Ltd.,
Keywords: Dry Etching, Inductively Coupled Plasma, InP,
Backside Vias
Abstract
For the last several years,
there has been great interest in InP HBTs due to the attractive properties of
InP and its lattice matched materials used for high-speed digital circuit
fabrication. Based on the successful introduction of high performance circuits
on GaAs with backside vias, the same approach has been used for InP. The
purpose of this work is to present results from dry etching of deep backside
vias in InP in a high density, inductively coupled plasma reactor. All etching
has been carried out on 3-inch wafers mounted on sapphire carriers. Our results
show ~100 µm deep vias with good profiles, average InP etch rates of 1.5 µm/min and selectivities of InP to mask
(photoresist) =10:1. This
process is acceptable to introduce to our manufacturing environment.