Cycle Time
Reduction During Electroplating of Through Wafer Vias For Backside
Metallization of III-V Semiconductor Circuits
Dennis Anderson,
Heather Knoedler, Shiban Tiku
Skyworks Solutions
Inc.,
[dennis.anderson or
heather.knoedler or shiban.tiku @skyworksinc.com
phone: 805- 480-4274]
Keywords: through wafer vias, cycle time reduction,
electroplating, gold-sulfite
Abstract:
The cycle time for
electroplating through wafer vias (TWVs) has been reduced by 50% with little to
no loss in plating thickness and uniformity by adjusting the plating parameters
through design of experiments (DOE) studies. By optimizing the mechanical
parameters of the plating tool, the power supply parameters, and the bath
component concentrations, the studies showed that the current density could be
doubled.