Breaking the 1000 Wafer/Week Barrier Through Substrate Via Process

K.M. Adam, L.S. Klingbeil
Motorola Semiconductor Products Sector
Compound Semiconductor One; CS-1
2100 E. Elliot Road, MD: EL-609, Tempe, AZ  85284

The demand for compound semiconductor devices with low inductance through substrate via holes continues to increase as operation frequencies climb.  However, the process used to fabricate through substrate via holes is not considered a high volume manufacturable process by silicon standards.  The mechanical nature of the process and the severity of etching a via 25 to 100 times deeper than a traditional interconnect via presents challenges to maximizing volumes and keeping costs down.

Processing aside, manufacturing philosophies and monitoring tools can help increase volumes and lower costs considerably.  These include the practice of Theory of Constraints or TOC, and the application of a standardized equipment performance metric. Overall Equipment Efficiency (OEE).  Together with innovations from the equipment industry, high volume manufacturing of through substrate vias can be achieved.

 

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