Process Modelling and Simulation for GaAs P-HEMT Gate Improvement and Control

S K Jones, D J Bazley, D R Brambley, P A Claxton
I R Cleverley, I Davies, R A Davies, C Hill, W A Phillips
N M Shorrocks, M Stott, K Vanner, R H Wallis, D J Warner
Caswell Technology, Marconi Caswell, Ltd

The drive to increase yield and volume of GaAs manufacturing has motivated the increased use of process and device modeling to understand and control sources of process variation and to improve device design for flexible manufacturing. Adapting tools and techniques developed for VLSI silicon, we have implemented a Technology CAD procedure for evaluation of process and device design. The purpose of this paper is to present results on how this procedure is being used to support our 150mm foundry upgrade, with specific focus on the Lg=0.2 micron Pseudomorphic HEMT process.