Development of Circuits in Indium Phosphide for Communication at 40Gbit/s and Above.

 

Alan D. Huelsman

Vitesse Semiconductor Corp.

 

Abstract

 

Vitesse has developed an indium phosphide (InP) heterojunction bipolar transistor (HBT) process and used that process for the fabrication of 40Gbit/s communication circuits. The process is run in the Vitesse 4 wafer fab located in Camarillo, Ca which is dedicated to the production of InP circuits. Transistor performance of 150GHz for ft and fmax are achieved with a conservative mesa isolated NPN structure that leaves room for future advancements through device scaling. Single (SHBT) and double (DHBT) transistor structures have both been fabricated with success. PIN photodetectors have also been built in this process allowing the integration of optical functions. Circuits discussed here have been built in the SHBT process. The process is designed around high yield manufacturable methods which have produced circuits with excellent yield. Circuits have been designed using both distributed and lumped element architectures with success. A building block approach has been used to maximize yield, schedule, and performance success. At this time all key building blocks for the OC-768 physical layer have been demonstrated. A TIA, limiting amp, PIN diode, 4:1 MUX/DEMUX pair, and a driver with 3.5V pp swing have all been demonstrated in the lab and are now being sampled to customers.

 

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