Impact of Backside Via Dimension Changes on High Frequency GaAs MMIC Circuit Performance

P. Nam, R. Tsai, D. Davison, B. Allen, M. Barsky, R. Grundbacher, R. Lai and S. Olson

Northrop Grumman Space Technology, Microelectronic Product Center,

Redondo Beach, CA 90278

Tel: (310) 813-8820, Fax: (310) 812-9501, Email: peter.nam@trw.com

 

Keywords: Backside Via Etching, RIE, ICP, Via Inductance, PHEMT, LNA

 

Abstract

This paper covers the impact of backside via dimension changes by utilizing ICP etching on the high frequency GaAs LNA circuit performance. New ICP tool offers improved repeatability and control of via size as compared to the existing RIE tool, but the via dimension significantly changed. Slight peak gain frequency shift to lower and gain slope change were observed by utilizing ICP etching, however, a narrow gain distribution was observed. Overall, ICP and RIE is not comparable process where the change of via dimension and consequent inductance change is sensitive to the circuitperformance. Via dimension changes must be accounted for designs

 

 

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