Eliminating Pillars During GaAs Via Etch Formation

R. Westerman 1 , D. Johnson 1 , F. Clayton 2

Unaxis USA, Inc., St. Petersburg, FL 33716, russ.westerman@unaxis.com, (727) 577-4999

Motorola Inc., Tempe, AZ 85284, fred.clayton@mot.com

 

Abstract

Pillar formation in GaAs vias is potentially harmful to reliable metallization. Pillar formation can arise from a number of causes including residues from upstream operations, material effects, and the plasma etching process. Using mechanical GaAs wafers, the plasma etch process contribution was partitioned through surface analysis and designed experiments. Pillar formation can be reduced through the use of higher Cl2 flows, lower process pressures, and higher ICP powers. Lower RF bias powers during the etch initiation step also significantly reduced pillar formation.

 

 

10-5.pdf             Return to TOC