High Yield Lithography and Wafer Handling Methods for Reliable Backside Processing of Brittle III-V Materials

C. Schaefer 1 , V. Dragoi 1 , S. Farrens 2 , M. Wimplinger 1 , P. Lindner 1

1 EV Group E. Thallner GmbH, DI Erich Thallner Straße 1, A-4780 Schärding, Austria 2 EV Group Inc., 3701 E. University Drive, Suite 300, Phoenix, AZ 85034, USA

E-mail: C.Schaefer@EVGroup.at, Phone: +43 7712 5311-0

 

Keywords: thinned III-Vmaterials, automated backside lithography, automated temporary bonding and de-bonding

 

Abstract

This paper focuses on state-of-the-art backside lithography technology for advanced applications in compound semiconductor material processing. The need for thinned III-V materials with a thickness below 100 or even less than 50 micron in high frequency as well as power devices creates new challenges in the handling of those extremely fragile and costly substrates. Breakage of such brittle substrates during manufacturing can create significant expenses for high volume manufacturers. The risk of damage is increased also by the multiple processing steps required, and again when using backside processing for vias generation. This paper describes solutions for automated backside lithography processing in terms of handling and pre-alignment as well as the reliable preparation of those materials prior to the backside processing sequence via automated temporary bonding/debonding technologies using a dry adhesive thermal release film. Furthermore recent results on alignment accuracy during the backside lithography will be presented and the TTVs achieved by different temporarily bonded material combinations.

 

 

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