Characterization and Control of Galvanic Corrosion During GaAs Wafer Photoresist Processing

J. Moore, H. Hendriks*, and A. Morales*

General Chemical - Electronic Materials, 2340 Bert Drive, Hollister, CA 95023, (831) 630-6202, jmoore@genchemcorp.com

*M/A-COM: Tyco, 100 Chelmsford Street, Lowell, MA 01851 USA, (978) 656-2562, hhendriks@tycoelectronics.com

 

Keywords: galvanic corrosion, noble metal, photoresist stripper, gallium arsenide (GaAs), and metal lift-off

 

Abstract:

The occurrence of galvanic corrosion on compound semiconductor substrates with exposed metal has been observed as deleterious device effects.1-7 Noble metals, e.g. gold, platinum, etc., in contact with exposed GaAs can induce undesired galvanic etching during wet process steps and result in surface irregularities that adversely affect yield. This phenomenon can occur when stripping photoresist using an aggressive wet chemistry. Rinsing steps that use de-ionized (DI) water can make matters worse.1-3,5-7 Control and minimization of compound semiconductor and metal corrosion has received much attention in wafer fabrication. Some facilities have used electrical measurements or SEM (scanning electron microscopy) observations to characterize and alleviate corrosion issues. For photoresist mask strip steps, some facilities avoid problems by choosing a corrosion-safe chemistry, which may not necessarily provide optimum performance. Unfortunately, challenges in removing tenacious organic residues exist, especially from deep ultraviolet (DUV) and hard-baked exposures. Although residue removal typically involves more aggressive chemistries, substrate protection and cleaning efficacy can be achieved. Using novel chemistry formulations and process techniques, galvanic corrosion can be controlled. This paper characterizes GaAs based corrosion near ohmic and gate metal layer features and shows how it varies with the choice of chemistry and the addition of water due to absorption or rinsing.

 

 

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