Sub-Surface Damage Removal in Fabrication & Polishing of Silicon Carbide

C.Martin, Dr. T.M. Kerr, W. Stepko, Dr. T. Anderson

1II-VI, Inc. 20 Chapin Rd., Suite 1005, Pine Brook, NU07058 USA

973-227-1551; Fax -973-227-8658; email: cmartin@ii-vi.com

 

Keywords: Silicon Carbide, CMP, Sub-Surface Damage

 

Abstract

Silicon Carbide (SiC) is emerging as a promising substrate for systems which leverage the low lattice mismatch with Gallium Nitride (GaN), high power density, heat dissipation and radiation hardness properties unique to this semiconductor.Wafer fabrication and polishing of SiC substrates poses processing issues as a result of the materialís high Mohs hardness (~9.25), and chemical inertness.Particularly important to epitaxial layer nucleation on these wafer surfaces is an atomically smooth finish free of sub-surface damage, which is invisible to most inspection methods.Prime damage-free surfaces will ideally exhibit bi-layer terraces corresponding to plane (0001) edges.II-VI has achieved such damage-free surfaces by closely monitoring damage through molten KOH etching and optical characterization, and developing a chemo-mechanical polish (CMP) process that effectively reveals this damage while simultaneously removing it.

 

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