InP Backside Via Formation Using High Etch Rate and Low Temperature HI-Based ICP Etching

Kenji Kotani, Takeshi Kawasaki, Seiji Yaegassi, and Hiroshi Yano 
Eudyna Devices, Inc. 
1, Kanai-cho, Sakae-ku, Yokahama 244-0845, Japan 
Phone: +81-45-853m Fax: +81-45-853-8170, Email: k.kotani@eudyna.com

InP-based devices have shown great potential in realizing high-speed Monolithic Millimeter-wave Integrated Circuits (MMICs).  Backside via is one of the most important elements for high-speed MMICs.  We have demonstrated high etch rate and low temperature InP etching using HI-based Inductively Coupled Plasma (ICP).  A Dry Film Resist (DFR) with high temperature tolerance was employed as an etching mask.  Using these technologies, InP backside via formation process was simplified.  After via formation, electric properties were evaluated over a 3-inch diameter wafer.  High uniformity and reproducibility enough for practical applications were obtained.  InP, Backside Via, HI, Inductively Coupled Plasma Etching

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