Trap Analysis of GaN-Insulated-gatge-HEMT for High Reliability

Toshihide Kikkawa, Masahito Kanamura, toshihiroOhki, Kenji Imanishi,Kozo Makiyama, Naoya Okamoto, Naoki Hara and Kazukiyo Joshin

 
Fujitsu Limited and Fujitsu Laboratories Ltd.

10-1 Morinosata-Wakamiya, Atsugi, Kanagawa, 243-0197, Japan

kikkawa.toshi@jp,fujitsu.com

Phone: +81-46-250-8243

 

In this paper, we describe the analysis of trap issues of the GaN insulated-gate HEMTs (MIS-HEMTs) to obtain high reliability. SiN was used for the insulated layer in this study. Trap effect was investigated using the pulsed I-V measurement, focusing on the effect of the initial gate and drain voltage. Current collapse could be suppressed by optimizing the heterointerface between SiN and GaN-HEMT layer. However, we found that the increase of maximum current (Imax) was observed when the initial state was a forward gate bias condition with a high electric field, such as an initial gate voltage of 2 V and a drain voltage of 50 V. This Imax shift phenomena never occurred at the Schottky-gate HEMT structure. We confirmed that Imax shift could be suppressed by optimizing SiN layer quality. This measurement method is essential for developing and optimizing the reliability of GaN-MIS-HEMTs for mass-production.

 

05c.PDF              Return to TOC