0.10 µm Ion-Implanted GaAs MESFETs with Low Cost Production Process

M. Watanabe, D. Fukushi, H. Yano, and S. Nakajima

Eudyna devices Inc. 1, kanai-cho, Sakae-ku, Yokohama, 244-0845 Japan, Phone: +81-45-853-8153, Fax: +81-45-853-8170, E-mail: m.watanabe@eudyna.com

Keywords: Ion- implantation, Collimated Sputtering, GaAs MESFET, fT, fmax

Abstract

We have successfully fabricated 0.1 µm gate GaAs MESFETs using a low cost process. The result was obtained from optical lithography, resist etching, and ion-implantation technologies based on Single Resist layer Dummy gate (SRD) process. The novel feature of the SRD process is forming a sub-quarter micron gate with conventional optical lithography. We have obtained a 0.18 µm gate using this process. Achieving a smaller gate length of 0.1um is very difficult with this process due to the pattern size shift of the sputtered SiO2 opening. In this study, we use a collimated sputtering technique in the SRD process to reduce the pattern size shift. As a result, the pattern size shift of the SiO2 opening decreases to 0.02 µm allowing a 0.1 µm gate length to be obtained by using conventional optical lithography. The high-speed performance of fT =81 GHz and an fmax of 142 GHz are achieved with the refined SRD process.

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