Fabrication of a robust high-performance floating guard ring edge termination for power Silicon Carbide Vertical Junction Field Effect Transistors

Victor Veliadis, Megan McCoy, Ty McNutt, Harold Hearne, Li-Shu Chen, Gregory DeSalvo, Chris Clarke, Bruce Geil*, Dimos Katsis*, Skip Scozzie*

Northrop Grumman Advanced Technology Laboratory, MS 3B10, Linthicum, MD 21090 *U.S. Army Research Laboratory, 2800 Powder Mill Road, Adelphi, MD, 20783-1197, USA

Email: victor.veliadis@ngc.com, Phone: (410) 765-7037

Keywords: VJFET, silicon carbide, power switch, guard rings, edge termination, inverter

Abstract

Vertical Junction Field Effect Transistors were manufactured on 4H-SiC three-inch wafers for 1200 V power conditioning applications. To ensure high breakdown voltage yields, a robust high-performance guard ring edge termination was designed and fabricated. Manufacturing of the self-aligned guard ring structure requires relatively fewer processing steps and the occurrence of broken rings that lead to premature voltage breakdown is eliminated. The p+ guard rings are formed by multiple energy ion implantations, occurring simultaneously with the implantation of the p+ gates. The self-aligned property ensures excellent line-width control and precision in the distance of the first ring from the edge of the mesa. By optimizing the number of guard rings, their widths and spacings, and the proximity of the first guard ring to the main junction, breakdown voltages of 93% of the SiC material limit were obtained. This enables high voltage operation with minimum associated on-state resistance. Compared to the Multiple Junction Termination Extension technique, guard ring edge termination is more cost effective for manufacturing as it requires fewer processing and implantation steps.

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