Post-Si CMOS: III-V n-MOSFETs with High-k Gate Dielectrics

Yanning Sun,1 S. J. Koester,1 E. W. Kiewra,1 J. P. de Souza1, N. Ruiz,1 J. J. Bucchignano,1 A. Callegari,1 K. E. Fogel,1 D. K. Sadana,1 J. Fompeyrine,2 D. J. Webb,2 J.- P. Locquet,2 M. Sousa,2 R. Germann,2

1IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598, USA, yansun@us.ibm.com, (914) 945-30832IBM Zürich Research Laboratory, CH-8803 Rüschlikon, Switzerland

Keywords: III-V, MOSFET, BURIED-CHANNEL, ENHANCEMENT-MODE, HIGH-K, DIELECTRIC

Abstract

As the end of Si CMOS scaling is approaching, III-V compound semiconductors have received renewed attention as the channel materials for future generation CMOS technology. We have reviewed the benefits, the opportunities, and the challenges of III-Vs for digital applications. We have also demonstrated functional enhancement-mode GaAs-, and InGaAs-channel MOSFETs, with high-1 gate dielectrics. The results show promise for realizing III-V MOSFETs for future VLSI logic applications.

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