Layout Design Rule Effects on Capacitor Reliability

James D. Oliver, Harlan C. Cramer, and Richard J. Porter
Northrop Grumman Electronic Systems
M/S 3K13, PO Box 1521
Baltimore MD 21203
j.oliver@ngc.com 410-765-0117
Keywords: Capacitor, Reliability, Dielectric Breakdown, Lifetime, Design Rules

Abstract
A test mask was constructed to evaluate the capacitor layout design rules and their affect on the capacitor yield and reliability. This detailed study, evaluating capacitor design spacings as well as dielectric thickness shows that even perceived large spacings of 2-5 um in the overlay of top and bottom plate metals
 
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