Thermal-Mechanical Characterization of Wafer Level Packaging Technologies

R. Sandhu, P. Chang-Chien, Mathew Parlee, B. Poust, T. Chung, R. Tsai, A. Noori, V. Temsevary, O.
Fordham, X. Zeng, K. Tornquist, D. Duan, T. P. Chin, and M. Barsky
Northrop Grumman Space Technology
One Space Park, Redondo Beach, CA 90278
Randy Sandhu, Email: rajinder.sandhu@ngc.com Tel: (310) 813-4815

Keywords: 3-D Integration, 3-D Heat Pipes, Heat Removal, Thermal-Mechanical Integrity

Abstract:
3-D passive thin film resistor heat removal test structures were fabricated on multi-layer wafer configurations to characterize and optimize vertical and horizontal heat removal in wafer level packaging technologies. Four layer heat removal test coupons with optimized thermal management design demonstrate a thermal resistance of less than 36ºC/W. Two layer test cells with DC interconnections and active device structures were also fabricated to evaluate and characterize the thermalmechanical integrity for 3-D integrated structures. The robust multiple layer construction demonstrates no measurable changes in DC resistance of interconnects or small signal performance of active devices after completing 10 thermal stress cycles from -55 to 125ºC. Results from 3-D x-ray computed tomography imaging will be presented to demonstrate advanced thermal-electrical-mechanical integrity analysis for multilayer structures.
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