Process Benchmarking of SiC Backside Via Manufacturing for GaN HEMT Technology

H.Stieglauer, G.Bödege, D.Öttlin, M.Ilgen, H.Blanck and D.Behammer

United Monolithic Semiconductors – GmbH, Wilhelm-Runge-Strasse 11, D-89081 Ulm, Germany Phone: +49-731-505-3075, Fax: +49-731-505-3005, E-mail: hermann.stieglauer@ums-ulm.de

Keywords: SiC, Via Hole, GaN HEMT, Laser Ablation, ICP Etching
Abstract

GaN technology is rapidly becoming of increased importance for many IC manufacturers. Backside processes are especially often challenging for GaN technologies due to the types of substrate material used. In comparison to GaAs and Si technologies, less knowhow exists for the integration of a via hole process in thinned SiC substrates with an active GaN EPI layer in a manufacturing area. In this work we present benchmarking of a SiC via hole process for GaN HEMT technology in terms of quality, integration and production points of view, tool investment and maintenance. Two process flows will be described and compared to each other. One flow utilizes a state of the art process with an ICP etch of the SiC using a hard mask and the other a blind hole process using a laser source with optimized parameters for a high SiC ablation rate. The major difference between these processes is that the ICP process etches via holes simultaneously and the laser ablate the vias sequentially.

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