SiC Backside Via-hole Process For GaN HEMT MMICs Using High Etch Rate ICP Etching

Naoya Okamoto, Toshihiro Ohki, Satoshi Masuda, Masahito Kanamura, Yusuke Inoue, Kozo Makiyama, Kenji Imanishi, Hisao Shigematsu, Toshihide Kikkawa, Kazukiyo Joshin, and Naoki Hara

Fujitsu Limited and Fujitsu Laboratories Ltd. 10-1 Morinosato-Wakamiya, Atsugi 243-0197, Japan
E-mail: naoya_okamoto@jp.fujitsu.com, Phone: +81-46-250-8242

Keywords: SiC, Backside via-hole process, ICP etching, GaN HEMT

ABSTRACT

We have demonstrated a SiC backside via-hole process for GaN HEMT MMICs using ICP etching at a high rate of about 2 μm/min, higher than any previously reported rate. We discuss pillars, microtrenches, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are significant issues related to the yield of via-hole fabrication. Finally, we describe the successful 3-inch backside via-hole process for GaN HEMT MMICs.

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