SiC Substrate Via Etch Process Optimization

Ju-Ai Ruan, Sam Roadman, Cathy Lee, Cary Sellers, Mike Regan

TriQuint Semiconductor, 500 W Renner Road, Richardson, TX 75080-1324 Phone: (972) 994-3842, e-mail: jruan@tqs.com

Keywords: SiC via etch
ABSTRACT  

SiC etch rates and etch selectivity to GaN have been studied under a range of RF plasma power conditions. Slightly higher etch rate and higher etch selectivity were obtained at increased coil RF power. Higher etch rate was also obtained at increased platen RF power, but at the sacrifice of decreasing etch selectivity. Substantial pillar formation was observed when coil RF power is below certain limit. Pillar formation during SiC etches due to variation of process conditions was also studied with methods to reduce pillar formation discussed. We observed that by properly modifying pre-etch clean and etch processes, systematic pillar formation can be avoided.

 

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