The Development of 0.5-_m High Linearity and Good Thermal Stability

AlGaAs/GaAs HFET for Wireless Infrastructure

 

Cheng-Kuo Lin, Shu-Hsiao Tsai, Chao-Hong Chen, Ru-Yong Chen, Jen-Hao Huang and Yu-Chi Wang

WIN Semiconductors Corporation

No. 69, Technology 7th Rd., Hwaya Technology Park, Kuei Shan Hsiang,

Tao Yuan Shien, Taiwan 333

Phone: +886-3-3975999 ext. 1555, e-mail: cklin@winfoundry.com

 

Keywords: GaAs, HFET, Linearity and Thermal Stability

 

Abstract

Heterostructure FETs (Doped-Channel FETs) have been widely used for high linearity requirement system such as digital wireless communication infrastructure due to its excellent electron confinement ability and superior Schottky barrier height characteristics.

In this paper, we report the development status of the 0.5-_m gate-length double-recess GaAs HFET. A 1.2-mm device can achieve P1dB output power of 21.5 dBm with a third order intercept (TOI) point of 43 dBm, where device was biased at Vds=5V and 50% of Idss operation at 0.5 GHz frequency operation. In this technology, it is critically important to develop a high thermally reliable device. After optimization transistor layout configuration such as and gate-to-gate pitch and specific wide-recess etching process, there is no obviously current degradation was observed on 4.8-mm devices, hich are operated at Vds=8V and 50% of Idss peration under 75 C ambient-temperature for 168 hours.

 

 

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