Wafer Level Bump Technology For III-V MMIC Manufacturing

 

X. Zeng; P. Chang-Chien; K. Hennig; C. Cheung; T. Chung; G. Akerling; J. Gan; J. Uyeda; M. Barsky;

A. Oki

Northrop Grumman Aerospace Systems

One Space Park, Redondo Beach, CA90278

Tel: (310) 812-2644, Email:xianglin.zeng@ngc.com

 

Keywords: Solder Bump; Copper Bump; Shear Strength; MMIC

 

Abstract

Wafer level bump technology that is compatible to III-V MMIC technology is reported. Two different wafer level bump technologies are presented in the paper. One is solder ball bump and the other is copper bump. Both are fully compatible with existing III-V MMIC backside manufacturing processes. Silicon nitride, deposited at room temperature, is used as solder mask and shows excellent solder blocking capability. UBM (Under-Bump- Metallization) materials were specially selected for their solid diffusion barrier characteristics and strong adhesion between bump and MMIC backside metal pad. Bump planarity, shear strength and solderability are extensively characterized, and benchmarked with industry specifications

 

 

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