Elimination of Yield Loss Due to Rogue Polyimide Vias

 

David Crawford, Yelda Recsei, Manjeet Singh, Dragana Barone, Samuel Mony, and Shiban Tiku

Skyworks Solutions, Inc.

2427 West Hillcrest Drive, Newbury Park, CA 91320

Email: david.crawford@skyworksinc.com

(805) 480-4360

 

KEYWORDS: PLASMA ETCH, POLYIMIDE, RESIST FLOW, VIA, YIELD LOSS

 

Abstract

Polyimides are high performance polymer dielectrics commonly used in III-V semiconductor fabrication. These have a desirable planarizing property and have good dielectric and thermo-mechanical properties, such as low dielectric constant, low stress, high modulus and chemical resistance. The planarizing characteristics of polyimides are beneficial and useful when the substrate has significant topography, such as gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) Power Amplifier (PA) devices, which have deep mesas. However, dry etching of polyimides can be a challenge due to lack of etch selectivity with photoresist and a tendency of polyimides vias to become enlarged during plasma processing, a large overetch cannot be used. In this paper, we discuss the case of “rogue” vias that did not open during the etching of polyimide used between Metal-1 and Metal-2, while the majority of the vias were open.

 

 

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