Compound Semiconductor Based Tunnel Transistor Logic

 

Suman Datta, S. Mookerjea, D. Mohata, L. Liu, V. Saripalli, V. Narayanan and T. Mayer

The Penn State University, University Park, PA, USA, email: sdatta@engr.psu.edu

 

Keywords: Tunnel FET, InGaAs, logic, SRAM

 

Abstract

In this invited talk, we introduce a new transistor architecture based on inter-band tunneling mechanism as a step towards exploring steep switching transistors for energy efficient logic applications. While others have researched on developing these transistors in the Si, Ge and their alloys, we have focused specifically on narrow gap compound semiconductor (CS) systems to develop tunnel transistors. We address the following topics regarding the CS-based tunnel transistor architecture: a) the choice of appropriate materials to tune the transfer characteristics over a specified gate voltage swing b) the characteristic screening lengths in these device essential for scaling, c) an effective way to estimate the switching speed of tunnel transistors, d) digital circuit design methodologies utilizing tunnel transistors.

 

 

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