Low RF power SiC Substrate Via Etch

 

Ju-Ai Ruan, Sam Roadman, Wade Skelton

TriQuint Semiconductor, 500 W Renner Road, Richardson, TX 75080-1324

Phone: (972) 994-3842, e-mail: jruan@tqs.com

 

Keywords: SiC via etch, pillars

 

Abstract

Effect of coil RF power on pillar formation in SiC via etch using ICP etching process has been studied. It was observed that when using only a typical etching chemistry such as SF6 in the reactant and as coil RF power is reduced to certain threshold, pillar density starts to increase drastically. By properly modifying the etching process especially the reactant mixture, it is possible to obtain pillar free result at substantially reduce coil RF power. This selection of parameter space enables the wafer to stay at relatively low temperature during SiC via etch. This opens up new alternatives to simplify the backside process.

 

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