Stress Suppression of Backside Metal in GaAs Devices

 

Koichiro Nishizawa, Katsuhisa Kitano, and Hirohumi Nakano

High Frequency & Optical Device Works, Mitsubishi Electric Corporation

4-1, Mizuhara, Itami, Hyogo 664-8641, Japan

TEL +81-72-784-7401, FAX +81-72-780-2683,

E-mail Nishizawa.Koichiro@ds.MitsubishiElectric.co.jp

 

Keywords: Backside electrode, Viahole, Plating, Stress, Nickel, Palladium

 

Abstract

In a Ni-P/Au electroless plating backside electrode, the stress of a thin Ni P film induced by annealing has been investigated using Stress gage, AES depth profile, X-ray diffraction measurements. Over around 100ºC temperature annealing, Ni diffusion was observed and the stress increased. With Ni diffusion, the Ni-P layer changed to P rich composition and to crystal from amorphous. The stress was caused by the crystallized Ni- P layer and the Ni diffusion layer. The increase of the stress is effectively suppressed by inserting the Pd barrier metal under Ni-P. The Pd/Ni-P/Au backside electrode makes it possible to form highly uniform and highly thermally stable metallization through via-hole on GaAs substrate.

 

 

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