EM Simulation and Development of Wafer Level Micro-packaging Technique for

GaAs-based RFMEMS Switches

 

Sandeep Chaturvedi1, Member, IEEE, Sangam V. Bhalke1, Mahadeva Bhat. K. 2, G. Sai Saravanan1, R.

Muralidharan1, Member, IEEE, Shiban K. Koul3, Senior Member, IEEE

1Gallium Arsenide Enabling Technology Center (GAETEC), Vignyana Kancha Post, Hyderabad-500069, India

2Solid State Physics Laboratory, Timarpur, Delhi-110054, India

3Center for Applied Research in Electronics, IIT Delhi, New Delhi-110016, India

 

Keywords: RFMEMS, wafer level packaging, micro-cap, reactive ion etching, EM simulation

 

Abstract: We present here a technique for wafer level micro-packaging of GaAs based RFMEMS switches. The developed technique is simple yet effective as it has a very minimal effect on the switch performance. Effects of package cavity height and physical properties of the cap material have been analyzed by full wave simulation and the optimal parameters were used during fabrication.

 

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