Advanced Semiconductor on Insulator Substrates for Low Power and High Performance Digital CMOS applications

Bich-Yen Nguyen, Mariam Sadaka, Nicolas Daval, Walter Schwarzenbach, Cecile Aulnette, Konstantin Bourdelle, Christophe Maleville, Carlos Mazure
SOITEC, Parc Technologique des Fontaines, Bernin 38926 Crolles Cedex, France


The concept of shrinking semiconductor device dimensions according to Moore’s law has been the mainstay of CMOS integrated circuit over many generations of technology and continues today relatively unabated. However, it has become increasingly difficult to scale CMOS transistors beyond 130nm, yet still maintain high drive currents and reduce supply voltage (Vdd). Therefore, much attention has been focused on high mobility channels that exhibit increased inversion layer mobility and higher carrier velocities, especially for boosting performance of the short channel devices. Such devices exhibit higher drive current enabling high speed, low power IC applications.

Starting at 90nm technology node, uniaxial strain have been implemented into existing Si CMOS process for boosting both N-type and P-type transistor, however the performance booster factor by the uniaxial stressors and even with biaxial strain has reduced with technology scaling.

From this viewpoint, attention has recently been paid to III-V and Ge channels beyond strained-Si technologies. This new III-V high-mobility materials are expected to replace silicon in the channel of transistor for further boosting performance and/or reducing the Vdd for lowering the power consumption for IC circuit. As such, MOSFETs using these new materials must be fabricated on Si substrates in order to fully utilize the Si CMOS platform, meaning the necessity of the co-integration of III-V/Ge on Si. This heterogeneous integration is expected to realize novel LSIs utilizing a variety of device families along More Moore, More-than-Moore and Beyond-CMOS approaches.

In this paper we will review the latest development including substrate engineering using the Smartcut technique (Figure 1), new device architecture and challenges for III-V/Ge CMOS co-integration on the Si platform.

Paper 10a.1.pdf