Investigation and reduction of leakage current associated with dielectric gate encapsulation in AlGaN/GaN HFETs

S. A. Chevtchenko, P. Kurpas, N. Chaturvedi, R. Lossy and J. Würfl
Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik (FBH),
Gustav-Kirchhoff-Str. 4, 12489 Berlin, Germany
e-mail:, Tel.: +49 30 6392 2674, Fax.: +49 30 6392 2685

Keywords: AlGaN/GaN HFET, HEMT, dielectric passivation, leakage current


The use of dielectric surface passivation in AlGaN/GaN technology is stipulated by improvement in dc/rf dispersion characteristics of GaN-based HFETs. [1] This passivation layer induces mechanical strain, which depends on type of dielectric, substrate and conditions of deposition. [2, 3] The most common choice of a dielectric is silicon nitride, which is also used for the two step lithography gate (“embedded” gate) realization. The MMIC fabrication process flow and the utilization of field plates in discrete microwave power transistors require encapsulation of the gate with the second dielectric layer. The application of the second dielectric layer, in turn, often results in an increase of the gate leakage current, which can be explained as a consequence of strain experienced by the gate. In this work changes in fabrication process flow and a number of AlGaN/GaN HFETs modifications were tested in order to reduce gate leakage currents associated with the second passivation layer.

The epitaxial structures GaN:Si/Al0.25GaN/GaN used for the fabrication of transistors were grown in-house on 3-inch diameter 4H semi-insulating SiC substrates by low-pressure metal-organic vapor phase epitaxy. A standard fabrication process employing Ti-based ohmic source and drain contacts and an Ir-based metallization to form the gate Schottky contact was used. The surface of the wafers was passivated with SiNx deposited by plasma enhanced chemical vapor deposition at 345°C. Gates with 0.5 μm length were defined by optical lithography and opened in SiNx by anisotropic reactive ion etching (RIE). On wafer isolation was done by N+ ion implantation yielding an isolation resistance ~ 1011 – 1012 Ω/□ at 100 V.

Wafers from the same growth run were used for all variations of the process flow sequence. The gate leakage currents were monitored on special transistors available at the early stages of the process. Two essentially different conditions in terms of strain in the vicinity of the gate finger were realized. Both conditions are represented schematically in Fig. 1.

Paper 10b.4.pdf