Self-Aligned In0.53Ga0.47As/InAs/InP Vertical Tunnel FETs

Guangle Zhou1, Y. Lu1, R. Li1, W. Hwang1, Q. Zhang1, Q. Liu1, T. Vasen1, C. Chen2, H. Zhu3, J. Kuo3, S. Koswatta4, T. Kosel1, M. Wistey1, P. Fay1, A. Seabaugh1, and Huili (Grace) Xing1
(1) Department of Electrical engineering, University of Notre Dame, Notre Dame, IN 46637, USA
(2) Saint Mary’s College, Notre Dame, IN 46556, USA
(3) IntelliEPI, Richardson, TX 75081, USA
(4) IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, USA
*Corresponding author: e-mail: gzhou2@nd.edu, Phone: +01 574 6311103

Keywords: Vertical FET, Tunnel FET, heterojunction, subthreshold slope, self-aligned

Abstract

A relatively simple and self-aligned vertical tunneling field-effect transistor (VTFET) process has been demonstrated using In0.53Ga0.47As/InAs/InP heterojunctions. At 300 K, the VTFETs show an on-current of 3 – 4.8 μA/μm and a minimum subthreshold swing (SS) of 220 mV/dec using Al2O3 gate oxide. The corresponding tunneling diodes exhibit negative differential resistance under forward bias over a range of temperatures, which confirms that the conduction mechanism is indeed band-to-band tunneling. This new self-aligned process is attractive to quickly realize and test VTFET designs.

Paper 13.6.pdf