Improved T-Gate Yield Using E-Beam Trilayer Resist Process

Huatang Chen, Andrew Ketterson, Marcus King, Keith Salzman, Vicki Milam, James Halvorson, Jan Campbell
TriQuint Semiconductor
500 W. Renner Rd Richardson, Texas 75080
Phone: 972-994-3942 Fax: 972-994-5768 Email: hchen@tqs.com

Abstract
Larger gate periphery power amplifiers are particularly sensitive to any anomalies in the gate formation process. The metal lift-off process, which is almost universally used in the III-V industry, is especially challenging since it is prone to formation of metal particulates and so-called “stringers”. Off-normal directional evaporation effects and insufficient retrograde resist profile can cause increased liftoff-related metal contamination especially at the edges the wafer. This contamination manifests itself as an increase in dc breakdown failures populated near the tops and bottoms of the wafers. Metal gate channel contamination (GCC) and whisker-like metal strings attached to the gate structure (wings) were found using STEM analysis at the testing failure site. These defects were attributed to the dc failures. To eliminate these defects, a trilayer resist process utilizing a single developer has been developed for the T-gate pattern definition step. We report on the improvement of the dc and final visual yields resulting from this new trilayer resist process.

Paper 8a.2.pdf