New On-Wafer Digital Laser Trimming Technique for Current
Adjustment of GaAs FET
Yukio Iwasake, Hidetoshi Furukawa, Tsuyoshi Tanaka and Daisuke Ueda
Semiconductor Device Research Center, Matsushita Electronics Corporation
3-1-1 Yagumo-Nakamachi, Morguchi, Osaka 570-8501, Japan
New on-wafer digital laser trimming technique has been developed for accurate and high-speed DC bias current adjustment of GaAs FET. The trimmable resistor is included in FET chip and small enough to be arranged between bonding pad area. The adjustment of bias-current is made by once exposure of pulsed YAG laser. Digital trimming can be performed during the wafer probe-testing, where the appropriate trimming pattern is selected by comparison of measurement and pre-set value. This technique has high throughput and no area penalty.