Zero-Offset Low-Knee-Voltage GaInP/GaAs Collector-up
Tunneling-Collector Heterojunction Bipolar Transistors for High-Efficiency High
K. Mochizuki, R. J. Welty, P.M. Asbeck
ecE Dept., University of California, San Diego, 9500 Gilman Drive, La Jolla, CA 92093-0407
*On leave from Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo 185-8601, Japam
We have developed a novel heterojunction bipolar transistor (HBT) structure, the collector-up tunneling-collector HBT (C-up TC-HBT), that minimizes the offset voltage VCE, sst and the knee voltage Vk. In this device, a thin GaInP layer is used at the base-collector junction to suppress hole injection into the collector. A collector-up structure is used because of the observed asymmetry of the band discontinuity between GaInP and GaAs depending on growth direction. Fabricated 120 x 120-mm2 C-up TC-HBT's showed almost zero VCE, sat (5 to 10 mV) and a very small Vk of 0.34 V at 0.5 kA/cm2, indicating that they are attractive candidates for high-efficiency high power amplifiers.