Optimization of HIGFETs on LT-GaAs Buffer

J.K. abrokwah, M. Sadaka, B. Bernhardt
Motorola Inc., 2100 E. Elliot rd., Tempe, AZ  85284

The application of low temperature buffers in complementary HIGFET devices has been previously shown to improve the radiation hardness of HIGFET circuits (1) and enable good performing submicron P-channel devices and complementary circuits (2).  However significant degradation of N-channel FET performance is observed using the LT-buffers.  This paper describes optimization of the LT-buffer to reduce the device degradation




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