Electrophoretic Photoresist Application for High Topography Wafer Surfaces

James Tajadod, Henry Hendriks, John Klocke*, Antonio Morales, and Heather Rapuano

M/A-COM: Tyco, 100 Chelmsford Street, Lowell, MA 01851 USA(978) 656-2562, hhendriks@tycoelectronics.com

*Semitool, 655 West Reserve Drive, Kalispell, MT 59901 USA, (406) 752-2107, jklocke@semitool.com


Keywords: electrophoretic photoresist (EPR), liquid photoresist (LPR), topography, silicon-on-glass (SOG), gallium arsenide (GaAs), and vias



As wafer surfaces become topographically more challenging, achieving uniform resist coatings in deep vias, over high mesas,

and three-dimensional (3-D) features may no longer be possible using conventional, solvent based, spin-coated liquid photoresist (LPR). Thinning of the resist on the high areas and pooling of the resist in the deep areas are common problems. Electrophoretic photoresist (EPR) may be used to achieve conformal 3-D resist coverage over high topography regions, while maintaining the high resolution and wet etch resistance properties of spin-coated LPR. Also, EPR may offer a higher throughput than spin-coated LPR. This presentation will describe two distinct applications where conformal masking of high topography wafer surfaces is needed and achieved by using EPR. The first application involves a silicon-on-glass (SOG) device technology that requires conformal masking of retrograde silicon pedestal structures up to 170 Pm high. The second application is for GaAs wafer through substrate via holes. For high power GaAs devices, a solder-stop metal needs to be masked inside the via to prevent Au-Sn eutectic solder from wicking into the hole during the solder die attach step.1, 2



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