Study of Reactive Ion Etching Process to Fabricate Reliable Via-Hole ground Connections in GaAs MMICs
D.S. Rawal. V.R. Agarwal, H.S. Sharma, B.K. Sehgal, R. Gulati and H.P. Vyas
Solid State Physics Laboratory,
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Keywords: GaAs, MMIC, Backside Via Hole, Etching
Via-hole etching process in GaAs has been studied using reactive ion etching with CC12F2/CC14 chemistry. The effect of starting substrate surface, type of mask used and RIE process parameters viz, pressure and power on the surface morphology of etched wall and etch profile has been investigated. Extensive SEM characterization was carried out to study the surface morphology, etch depth and etch profiles. The starting polished surface with photoresist mask was found to give better surface morphology of the etched wall. The surface smoothness improved with increase in pressure but at the cost of anisotropy. Increase in power resulted in anisotropic etch profiles but with poor surface morphology. RIE process with 50 mTorr pressure and 200W power were found to give desired profile and acceptable surface smoothness. Finally these process parameters with photoresist mask and polished starting surface were implemented in MMIC via-process and MMICs with 50mm dia., 100mm deep, lwo resistance (~0.4W) via hole grounds were fabricated with yield >80%. The inductance offered by these via’s was ~25 + 5 pH, well within acceptable limits.