Process and Performance Improvements to Type-II GaAsSb/InP DHBT’s

Bemjamin F. Chu-Kung, Shyh-Chiang Shen*, Walid Hafez, and Milton Feng  Department of Electrical and Computer Engineering,
University of Illinois, Micro and Nanotechnology Laboratory,
208 N. Wright Street, Urbana, IL  61801
Phone: (217) 333-4048, Email:

*School of Electrical and Computer Engineering
George Institute of Technology , Center for Compound Semiconductors,
777 Atlantic Drive NW, Van Leer Building, Atlanta, GA  30332-0250

GaAsSb/InP type-II transistors have been fabricated with fT >325 GHz and fMAX > 275 GHz.  This work will examine the layer structure design criteria allowing the fT to improve from 244 GHz to 358 GHz and the effects this has on the corresponding fMAX.  Additionally, the process improvements to control the undercut into the active region during the base contact isolation etch will be discussed.  These modifications improved fMAX from 225 GHz to 279 GHz. 

Keywords:  HBT, InP, GaAsSb, DHBT

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