Edge Defined Lithography for Nano-scale III-N Field Effect Transistors

J.P. Long, C.Zeng, Y. Jin, D.W. Barlage, M.A.L. Johnson 
North Carolina State University
, Raleigh NC 
Email: dwbarlag@ncsu.edu

In this work we demonstrate a method by which sub-100 nm features can be fabricated using only conventional semiconductor processing and optical lithography techniques.  This methodology uses no e-beam in the process but has the potential to create lithographically located features at dimensions approaching 5 nm.  The successful process becomes an exercise in thin film process control, rather than lithography process control.  To achieve this, we present several of the key issues surrounding the optimization process required to implement this technology and to exploit fully its potential. 

Keywords:  Spacer Gate, Edge defined lithography, MOSFET, GaN

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