Yield Improvement of MESFET Circuits with Idd Ring-Like Pattern

Y.Z. Wang, P. Fowler
141 Mt. Bethel road, Warren, NJ 07059 
Phone: (908) 668-5000 Email: ywang@anadigics.com

Diesort yield loss caused by bias current Idd out of specification limits showing a ring-like pattern in our major MESFET products was investigated in the paper.  Process splits and DOE were used to identify the root cause of Idd ring-like pattern.  It was found that the Idd ring-like pattern was caused by gate gold plating process.  The higher plating current density interacting with anode diffuser ring in the plating system resulted in higher stress at the boundary layer in the filter holes.  Hence, the stress-induced piezoelectric effect caused Idd shifts to low at these areas. 

Keywords:  MESFET, Plating, Idd Current, Yield

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