III-V on Silicon for Future High Speed and Ultra-Low Power Digital Applications:
Challenges and Opportunities

Robert Chau

Components Research, Technology and Manufacturing Group, Intel Corporation
Address: Mail Stop RA3-252, 5200 N.E. Elam Young Parkway, Hillsboro, Oregon 97124-6497 USA
Phone: 503-613-6141. E-mail address: robert.s.chau@intel.com
Keywords: III-V on silicon, quantum-well transistors, high speed, ultra-low power, digital logic
This presentation highlights the challenges and opportunities of III-V on silicon for future high speed, ultra-low power digital logic applications. It describes the heterogeneous integration of III-V transistors, such as enhancement-mode InGaAs quantum-well transistors on silicon substrates using thin composite buffer architecture, and their comparison to state-to-the-art silicon MOSFETs in device performance at very low supply voltage (e.g. 0.5V). The status of recent progress towards overcoming the five grand challenges in making III-V applicable for future logic applications is also discussed.
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