Evaluating Device Reliability Using Wafer-level Methodology

Dorothy June M. Hamada and William J. Roesch
TriQuint Semiconductor Inc., 2300 NE Brookwood Parkway, Hillsboro, Oregon 97124-5300
Phone: (503) 615-9298 Fax: (503) 615-8903 Email: dhamada@tqs.com
Keywords: Lifetest structures, on-wafer, reliability testing


This paper demonstrates the viability of wafer-level methods as a means of evaluating device reliability using special reliability test structures and process control monitors (PCM). The results presented illustrate how this methodology can be employed to rapidly and effectively assess the impact of process or material changes on over-all reliability. The wafer-level methodology provides a quick feedback loop for the manufacturing group enhancing their ability to continuously improve on their processes.
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