Recessed JPHEMT Technology for Low Distortion and Low Insertion Loss Switch

Shinichi Tamari, Koji Wakizono, Yuji Ibusuki and Mitsuhiro Nakamura

LSI Device Technology Department, Kagoshima Production Division 1, Sony Semiconductor Kyushu Corporatio, Kagoshima Technology Center, 5-1, Kokubu Noguchikita, Kirishima-shi, Kagoshima, 899-4393 Japan E-mail:, Phone: +81-995-47-3739

Keywords: JPHEMT, Switch, Recess, SP10T


We have developed a novel junction pseudomorphic high electron mobility transistor (JPHEMT) with a gate-drain and gate-source (gate-drain/source) recessed structure, Recessed JPHEMT (R-JPHEMT), and achieved the small off-capacitance (Coff) of 161fF/mm by using the recessed structure as well as keeping the low on-resistance (Ron) of 1.4ohm-mm with a buried pn junction gate. In Addition, we achieved a significant improvement in harmonics and inter-modulation distortions (IMD) compared with the ones in a conventional JPHEMT. Thus, this device has an excellent Quality factor (Q), the product of Ron-Coff, and low distortion characteristics as a switching device. The very low Q makes it possible to design a multi-throw switch, SP10T. The IMD2 and IMD3 of this SP10T switch are below -110dBm with low insertion loss. This novel device has been developed by using the low cost, 6inch, high-volume mass production technology.

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