High Volume Test Methodology for HBT Device Ruggedness Characterization


Cristian Cismaru, Hal Banbrook, and Peter J. Zampardi

Skyworks Solutions, Inc., 2427 Hillcrest Drive, Newbury Park, CA 91320

cristian.cismaru@skyworksinc.com, 805.480.4663


Keywords: BVceo, snap-back, HBT, high-volume test, ruggedness



Developing rugged transistors requires careful consideration of the HBT’s collector design. In this work we present a test methodology for high-volume, in-line measurement of device ruggedness. This method is useful not only when developing new epitaxial structures for HBT devices, but also allows in-line monitoring of the device ruggedness for possible deviations due to epitaxial or manufacturing process variations. Moreover, the test is non-destructive.



5.1.PDF                        Return to TOC