Quilt Packaging: A robust coplanar chip-to-chip interconnect offering very high



David Kopp, M. Ashraf Khan, Scott Garvey, Kristen Anderson, Jason Kulick, Alfred Kriman,

Gary H. Bernstein*, and Patrick J. Fay

Center for Nano Science and Technology

University of Notre Dame

Notre Dame, IN, 46556

*Tel: 574-631-6269 Email: bernstein.1@nd.edu


Keywords: GaAs, Si, interconnect, bandwidth



A novel coplanar waveguide-based chip-to-chip interconnect scheme called Quilt Packaging (QP) has been developed. This technology enables extremely high speed integration of multiple chips on Si substrates. The demonstration of this technology in GaAs and InP is ongoing. With this technology, wiring delays associated with signal transmission from chip to chip are greatly reduced. The mechanical properties of QP at elevated temperatures are under study to improve reliability.



17.4 PDF                      Return to TOC