Type-II DHBTs Microwave Characterization and Air-bridge Isolation Etch Issues

Kuang-Yu (Donald) Cheng and Milton Feng
Department of Electrical and Computer Engineering · University of Illinois at Urbana-Champaign
Micro and Nanotechnology Laboratory · 208 N. Wright Street · Urbana, IL 61801
Phone: (217)244-3662, e-mail: dkcheng@uiuc.edu


The extraordinary carrier transport properties of InP-based transistors enable InP HEMT with 50nm gate length [1] and HBT with 12.5nm base thickness [2] to reach highest power gain cutoff frequencies (fMAX) and current gain cutoff frequencies (fT), respectively. In InP-HBTs development, vertical scaling of material has been used to reduce transit time. However, as depicted in Fig. 1, this scaling leads to decreasing breakdown voltages as material layers are scaled. The direct correlation between power gain cutoff frequencies and base-collector capacitance (Cbc) also explains the vertical scaling tradeoff between fT and fMAX.

In order for balanced fT/ fMAX performance with high breakdown voltages which are required for mixed-signal sub-millimeter wave circuit designs, type-II InP/GaAsSb DHBT with InP collector has been shown to be able to achieve high speed and high breakdown voltage simultaneously [3]. The type-II DHBT has higher breakdown voltage for a given collector thickness than InP/InGaAs type-I DHBT and SHBT devices as shown in Fig. 2. The advantage of a type-II GaAsySb1-y/InP band alignment over type-I InGaAs/InP DHBT is due to the fact that current blocking effect is eliminated at base/collector interface, enabling ballistic carrier injection into the collector to reduce collector layer transit time. Fig. 3 illustrates the material structure and energy band diagram of the UIUC graded-base type-II DHBT. The material was grown at University of Illinois using a gas-source MBE and the device structures presented in this work benefit from optimization of the compositionally-graded base growth conditions to facilitate higher carbon doping incorporation and high quality base-emitter interfaces. Sub-micron devices were fabricated with emitter widths as small as 200 nm and lengths ranging from 2-8 μm. Extrinsic parasitics are minimized using a self-aligned base-collector mesa etch with emitter sidewall spacer and by using an isolated base contact post. A device SEM image depicting these features is presented in Fig. 4. Record DHBT fT performance was achieved by vertically scaling the base and collector epitaxial layers to 20nm and 60nm, respectively. A device with emitter area 0.3×8 μm2 has fT = 680 GHz and simultaneous fMAX = 175 GHz when operated at room temperature. The same device measured at -37ºC has simultaneous fT = 745 GHz and fMAX = 205 GHz at current density JE = 8.3 mA/μm2 (Fig. 5). DC characteristics of the device are presented in Fig. 6, exhibit low offset voltage, small knee voltage progression, and 1kA/cm2 BVCEO = 3 V.

One of the most critical steps in the fabrication of sub-micron HBTs is device isolation. Its purpose is to minimize current leakage paths so that the resultant parasitic resistances and capacitances can be eliminated allowing for better microwave performance. The device isolation utilizes a wet chemical etch to clear the metal air-bridge which forms the interconnect between the base metal post and the active area of the device. The multiple epitaxial layers beneath the air-bridge require a complex wet etching process. The control of etching time is essential in order to generate uniform etching depth and thus, higher yield. In this paper we will discuss the influence of the isolation etch on the yield and performance of the sub-micron HBT along with process improvements to raise yield.

Paper 7a.3.pdf