In recent years, many GaN-based HEMTs for power amplification applications at Ka-band have been
reported. As gain affects the efficiency and consumption power of the device, to achieve high gain at this frequency it
is necessary that the gate-length of the device to be shorter than 0.2mm. However, fabricating short gate-length GaN
HEMT is difficult and complicated due to the increasing leakage current and lower breakdown voltage. Another factor
affecting the gain of the device is the source inductance. This inductance is contributed mainly by the physical layout
of the via and is independent on device's leakage current or breakdown voltage. In this paper, we reported on the
effects of via, in particularly its layout on the performance of the GaN HEMT device.
II. GaN Process
GaN HEMT device with gate-length of 0.2mm is fabricated on 3-inch SiC substrate. The HEMT structure is
based on Al0.3Ga0.7N/GaN epitaxial layers grown by MOCVD. Via-holes are formed by ICP-RIE and the back-side of
the wafer is thinned to 50mm by mechanical polishing. In this study, 50mm unit gate-width GaN HEMT devices with
various layouts of via patterns are fabricated and their small-signal gain characteristics are then compared.
First, GaN HEMT devices of 2, 8, 12 gate-fingers with side-vias layout as shown in figure 1 are compared.
As a result of the source terminal interconnections, these devices posses different source inductances. Figure 2 shows
the measured small-signal gain characteristics. It can be observed that the maximum frequency at which MSG is
maintained depends on the source inductance. At frequency higher than 30GHz, Type A (2 gate-fingers) achieved the
highest gain due to a smaller source inductance. However, for high-power applications, this device need to be
paralleled, whereby the total number of vias can increase the size of the device significantly.
Next, fixed gate width of 400mm (50mm x 8) devices with various via layout patterns as shown in figure 3
are compared. Figure 4 shows the measured small-signal gain characteristics of these devices. Comparing with
reference Type B (side-vias), Type D which has the vias near to the gate-pad achieved lower gain above 30GHz. This
can be explained by the physical layout connection extending from the source terminal to the via leading to an
increased in source inductance. To reduce this effect, Type E which has the number of vias increased, and Type F an
innovative layout using air-bridge to shorten the connection have been designed. These two types of patterns increased
the maximum frequency of the achievable MSG as compared to Type B. Moreover, both patterns can shrink the size of
the layout, an advantage for implementing compact high power devices.
Finally, a loadpull measurement at 31GHz is performed on Type E (4 via-holes) device biased at 24V. An
saturation output power of 32.6dBm (4.5W/mm), linear gain of 7.3dB and PAE of 41% has been achieved. Using this
layout pattern, an 8cells discrete power device (total gate-width=3.2mm) as shown in figure 6 has been designed at
Ka-band which will be followed up by a detailed measurement results.