The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

GaN power ICs on engineered substrates of Qromis substrate technology (QST^®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm² leakage current at 150 °C. The fabricated 36 mm power HEMTs with L_GD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

A single-layer optical filter made from thin film gallium phosphide (GaP) is envisioned and a fabrication flow is outlined, with current progress on process development reported. Ion-implantation is simulated and performed on bulk GaP with He⁺, followed by a field-assisted thermal bonding technique that simultaneously bonds a thin GaP film onto a borofloat glass substrate and removes the GaP substrate. The resulting thin films have consistent thickness, both within and between runs, and RMS surface roughness of < 10 nm. Dry-etch processes that further reduce the thin film material are characterized and designs for etching gratings into them are developed. This process is shown to be a reliable means of creating thin films of consistent thickness and smoothness in GaP, for the purpose of establishing visible wavelength filters for spectroscopic applications.

In this work we compare non-contact charge-voltage imaging and UV-photoluminescence (UV-PL) imaging of yield killer defects in epitaxial 4H-SiC wafers.  Two significant findings are based on macro- and micro-scale imaging, respectively.  1- Whole wafer images demonstrate that only a fraction of the UV-PL defects in triangular, downfall and carrot categories are electrically active. 2- Micro-scale images reveal similarities and differences between PL and electrical defect images.  Presented for the first time, micrometer resolution leakage patterns within triangular defects are consistent with the microstructure modeling in reference 1. The results imply that the depletion layer leakage within killer defects corresponds to exposed 3C-SiC polytypes. This leakage may be a consequence of the lower 2.2eV energy gap of 3C-SiC compared to 3.3eV in 4H-SiC.

GaN power ICs on engineered substrates of Qromis substrate technology (QST^®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm² leakage current at 150 °C. The fabricated 36 mm power HEMTs with L_GD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

GaN is a promising material for more efficient high frequency and high voltage power switching. However, GaN still is not the common material for power electronics due to immature substrate, homoepitaxial growth, and processing technology. Electroluminescence is a promising method to predict failure points due to high field stress, which can assist in the separation of inherent defects stemming from substrate quality, and from process-induced defects as well as identify problems related to proper edge termination design. In this work, we compare the Electroluminescence signatures of devices on inhomogeneous substrates to DC I-V behavior to demonstrate the utility of the technique for process monitoring.

It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

Metal–insulator–semiconductor p-type GaN high-electron-mobility transistor with an Al₂O₃/AlN deposited by atomic layer deposition was investigated. The selected insulator, AlN has been proven to have a good interface with GaN. A traditional p-GaN device without an Al₂O₃/AlN layer was processed for comparison. Due to the Al₂O₃/AlN layer, the gate leakage was lower, and the threshold voltage was higher, at 4.7 V. Additionally, excellent turn-on voltage was obtained. Furthermore, low current degradation and smaller V_TH shift at high temperatures was also observed. Hence, growing a good-quality Al₂O₃/AlN layer can achieve an enhancement-mode operation with superior stability and high gate swing region.

This work characterizes the effects of gate-length (L_G) scaling in a self-aligned gate (SAG) β-Ga₂O₃ MOSFET process. Additional performance gains are expected by extending the SAG process from large L_G to sub-micrometer dimensions.  This data incorporates L_G scaling down to 200 nm to improve device performance in Ga₂O₃ SAG MOSFETs using a stepper lithography process to define sub-micron gate lengths.

Determination of reliability performance over time requires an accurate understanding of device junction temperature, not only in customer use condition, but also during production test and burn-in. Through carefully designed and executed LIV (L=Light, I=current, V=Voltage) measurements and a modeling framework where optical power, thermal and electrical device parameters are interrelated, the laser diode junction temperature, as confirmed by wavelength shift measurements, is obtained via regression of a non-linear self-consistent equation.  Modeled parameters include both threshold current and slope efficiency junction linear temperature dependence coefficients/constants, as well as a thermal impedance factor.

The etching of uniform, repeatable GaAs/AlGaAs mesas is an important step in manufacturing VCSELs. This paper presents a high uniformity, low foot etching of mesa structures on 6” wafers. The improved uniformity permits the use of production-friendly optical endpoint techniques which can be used to stop on a specific layer in the VCSEL structure.

GaN power ICs on engineered substrates of Qromis substrate technology (QST^®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm² leakage current at 150 °C. The fabricated 36 mm power HEMTs with L_GD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

Typical n-type ohmic contact formation for GaN material systems requires high-temperature thermal processes. The high-temperature process often leads to a rough surface after the annealing step. Low-annealing-ohmic contact is advantageous to prevent undesired surface roughening on the metal stack during this thermal process.  We report an approach to achieve low contact resistance on n-type GaN layers using a nitrogen plasma and a conventional Ti/Al-based metal stacks.  We observed an as-deposit ohmic contact behavior on the n-type contact with a specific contact resistance (r_c,sp) in the mid-E-6 Ω∙cm² range.  The r_c,sp was further reduced to  6.8E-7 Ω∙cm² after an annealing step at 600 ^oC.

In this work fabrication of MISCAP structures was achieved on n-type gallium nitride using atomic layer deposited silicon nitride as the dielectric layer and sputtered ruthenium contacts. Preliminary values extracted from C-f data suggests very high capacitance densities up to 3.18 μF∙cm^-2 and very high accumulation-mode field effect mobility, as high as 325 cm²V^-1s^-1 at a bias voltage of 2.5 V.

GaN power ICs on engineered substrates of Qromis substrate technology (QST^®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm² leakage current at 150 °C. The fabricated 36 mm power HEMTs with L_GD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

We present a novel heterogeneous photonic integration of III/V on silicon by using epitaxial regrowth on III/V-on-Si wafer bonded substrates. This integration method decouples the correlated root causes, i.e., lattice, thermal, and domain mismatches, which are all responsible for a large number of detrimental dislocations in the heteroepitaxial process.  The grown multi-quantum well vertical p–i–n diode laser structure shows a significantly low dislocation density of 9.5 × 10⁴ cm⁻², two orders of magnitude lower than the state-of-the-art conventional monolithic growth of III/V on Si. Hybrid InP-on-Si multi-quantum well lasers were successfully demonstrated with this heterogeneous integration and shown room-temperature pulsed and continuous-wave lasing. This generic concept can be applied to other material systems to provide higher integration density, more functionalities and lower total cost for photonics as well as microelectronics, MEMS, and many other applications.

The high growth of the EV/HEV market impacted significantly the wide bandgap semiconductor industry, creating new opportunities and a competition between SiC and GaN in many applications such as on-board chargers, DC-DC converters and main inverters. This paper provides an overview of SiC and GaN device technology, including Yole Développement’s understanding of the market’s current dynamics and future evolution of wide band gap materials compared to mainstream Silicon power electronics market.

The paper presents the market overview of different compound semiconductor such as GaN, GaAs, and InP impacted by the deployment of 5G in wireless infrastructure. The value chain from wafer and epitaxy to device level is covered, as well as technology and market trends and Yole’s forecast for the coming years.

In this work we present a systematic study on the conduction properties in vertical GaN trench MISFETs grown and manufactured on different free standing GaN substrates. It is shown that devices manufactured on ammonothermal substrates have superior conduction current density higher than 4 kA/cm², specific on‑state resistance as low as 1.1 ± 0.1 mWcm² and channel sheet resistance of 19.6 ± 0.9 Wmm. It is further shown that scaling these devices to large gate periphery is not limited by current spreading in the drift region, low channel mobility or by self‑heating. The conduction properties of devices manufactured on ammonothermal GaN substrates are found to be the most suitable for pulsed laser driving applications.

Transphorm is supplying N-polar GaN on SiC and sapphire epitaxial wafers for customers developing ultra-high performance RF and mm-wave electronics devices. The manufacturing process is SPC controlled and DOE optimized, and the wafers exhibit very high 2DEG electron mobility and excellent thickness and R_sh uniformities.

Transphorm is supplying N-polar GaN on SiC and sapphire epitaxial wafers for customers developing ultra-high performance RF and mm-wave electronics devices. The manufacturing process is SPC controlled and DOE optimized, and the wafers exhibit very high 2DEG electron mobility and excellent thickness and R_sh uniformities.

Traditional in-situ reflectometry sensing at blue (405 nm), red (630 nm) and NIR (950 nm) wavelengths cannot resolve variations in InAlGaN surface roughness or layer thickness with the precision necessary for effective in situ process control. LayTec has developed in situ reflectance metrology at 280 nm to address this need.

We report successful application of in situ UV reflect-ometry and curvature, distinguishing between various phases of strain relaxation and surface relaxation during non-pseudomorphic growth of Al_0.5Ga_0.5N on AlN/sapphire. Results were validated by XRD, TEM and AFM. Results illuminate the influence of reduced TDD on relaxation effects during growth of UVA and UVB LED structures.

Silicon carbide (SiC) semiconductor substrates are the foundation for revolutionary improvements in the cost, size, weight and performance of a broad range of military and commercial radio frequency (RF) and power switching devices. Due to the lack of a viable, native gallium nitride (GaN) substrate, semi-insulating (SI) SiC substrates are presently the substrate of choice for high power AlGaN/GaN High Electron Mobility Transistors (HEMTs) due to their near lattice-match to GaN, superior thermal conductivity and commercial availability. GaN has emerged as the technology of choice for RF power because of its superior output power capability compared to gallium arsenide.  Similarly, semi-conducting (N⁺) SiC substrates are required for fabrication of high voltage Schottky diodes and metal oxide semiconductor field effect transistor (MOSFET) power switching devices. Critical to this realization is the availability of affordable, high quality, large diameter SI and N⁺ SiC substrates for production of GaN and SiC power semiconductors.  SiC is unique in that bulk single crystals cannot be grown via traditional melt-based manufacturing processes such as Czochralski. Rather, a high temperature sublimation process is required. In the late 1980s, pioneering physical vapor transport research taking place at North Carolina State University ultimately led to the formation of Cree Research and subsequently the wide bandgap semiconductor industry.  U.S. Department of Defense investment in wide bandgap semiconductors, since the early 1990s, has easily exceeded $1B spawning an entirely new industry. The early days of SiC physical vapor transport growth research were fraught with perceived insurmountable technical challenges associated with micropipes, doping, polytype conversion, diameter expansion and crystalline defects. Despite this monumental crystal growth, technology hurdles, SiC substrates are presently manufactured at a cost and quality never thought possible. This paper highlights more than 20 years of AFRL sponsored development with II-VI aimed at positioning itself as a world-class manufacturer of SiC substrates.

The use of highly-doped thick cap layers is a common strategy to enhance the performance of GaInAs/AlInAs/InP High Electron Mobility Transistors (HEMTs) by reducing the Ohmic contact resistance (R_C). However, because of the high doping level, cap layers become very sensitive to processing steps performed before and during gate recess etching. In this paper, the sensitivity of gate recess etching on a 20 nm highly-doped GaInAs cap layer (doped 7.3 × 10¹⁹ cm^-3) is studied with respect to Ohmic contact type (annealed/non-annealed), chip size, gate finger length, and etchant choice. The use of very high cap doping levels exacerbates device and process scaling challenges. For example, the recess finger length dependence complicates multi-project wafer runs which would simultaneously include narrow finger HEMTs used in digital ICs and longer finger HEMTs used in microwave analog circuits.

The paper presents the market overview of different compound semiconductor such as GaN, GaAs, and InP impacted by the deployment of 5G in wireless infrastructure. The value chain from wafer and epitaxy to device level is covered, as well as technology and market trends and Yole’s forecast for the coming years.

This work describes an on-going effort to develop and mature a 140 nm GaN MMIC technology with a focus on efficient power amplification at frequencies ranging from DC to 50 GHz and a 90 nm technology targeted towards V- and W-band applications, and then release the technologies within a foundry process that is open to the DoD community.

A single-layer optical filter made from thin film gallium phosphide (GaP) is envisioned and a fabrication flow is outlined, with current progress on process development reported. Ion-implantation is simulated and performed on bulk GaP with He⁺, followed by a field-assisted thermal bonding technique that simultaneously bonds a thin GaP film onto a borofloat glass substrate and removes the GaP substrate. The resulting thin films have consistent thickness, both within and between runs, and RMS surface roughness of < 10 nm. Dry-etch processes that further reduce the thin film material are characterized and designs for etching gratings into them are developed. This process is shown to be a reliable means of creating thin films of consistent thickness and smoothness in GaP, for the purpose of establishing visible wavelength filters for spectroscopic applications.

In this work we present a systematic study on the conduction properties in vertical GaN trench MISFETs grown and manufactured on different free standing GaN substrates. It is shown that devices manufactured on ammonothermal substrates have superior conduction current density higher than 4 kA/cm², specific on‑state resistance as low as 1.1 ± 0.1 mWcm² and channel sheet resistance of 19.6 ± 0.9 Wmm. It is further shown that scaling these devices to large gate periphery is not limited by current spreading in the drift region, low channel mobility or by self‑heating. The conduction properties of devices manufactured on ammonothermal GaN substrates are found to be the most suitable for pulsed laser driving applications.

In this paper, we report our work on epitaxial growth of InAlN HEMTs for RF device applications.  InAlN HEMTs were grown on 8” high resistivity silicon substrates. Various characterization techniques were used to analyze the quality of the epi wafers. An average sheet resistance (R_sh) of 206Ω/□, with a uniformity of 1.5% (1s/average), indicated a high quality and uniform 2DEG. Hall measurement showed a high sheet charge density of 2.27×10¹³cm⁻² and a mobility of 1430cm²/(Vs). A pit free epi surface was obtained with optimized growth process of the active layers. T-gate RF devices fabricated on the InAlN epi wafers demonstrated an f_T of 250GHz and an f_MAX of 204 GHz, which are the record high values for GaN-based HEMTs on silicon.

Schottky devices play an important role in modern electronics. The forward biased current-voltage characteristics of such devices are linear on a semi-logarithm scale at intermediate bias voltages. However, the curve deviates from linearity at higher voltage primarily due to series resistance. The applied forward voltage on the device is equal to the sum of the voltage drops across the (1) junction, (2) series resistance, (3) depletion layer and (4) any parasitic resistive layer between the Schottky metal and the semiconductor. Therefore, the interface between the metal and the semiconductor plays an important role in determining the critical parameters of Schottky devices. In this investigation a controlled delay was introduced between the pre-metal clean and Schottky metal deposition steps of the fabrication process to study the effects of naturally grown oxide on the forward characteristics of the Schottky devices.  The results of the investigation indicate such delays cause significant increases in series resistance and ideality factor, as well as a decrease in barrier height.

In order to meet the forecast growing demand of n⁺ SiC material, wafer suppliers will need to implement new metrology techniques to allow the detection of crystalline defects and ensure the quality of their materials. Incumbent techniques such as KOH etching have been used for many years but remain very costly as the wafers cannot be processed further. Alternative techniques such as X-ray Diffraction Imaging (X-ray Topography) can be used to detect crystalline defects non-destructively but studies have been limited to synchrotron radiation which cannot be used as an in-line characterization. In this paper, Bruker have used novel equipment (Sensus-CS) to study the correlation between laboratory X-ray Diffraction Imaging and KOH etching performed at the University of Warwick.

In this work fabrication of MISCAP structures was achieved on n-type gallium nitride using atomic layer deposited silicon nitride as the dielectric layer and sputtered ruthenium contacts. Preliminary values extracted from C-f data suggests very high capacitance densities up to 3.18 μF∙cm^-2 and very high accumulation-mode field effect mobility, as high as 325 cm²V^-1s^-1 at a bias voltage of 2.5 V.

The use of highly-doped thick cap layers is a common strategy to enhance the performance of GaInAs/AlInAs/InP High Electron Mobility Transistors (HEMTs) by reducing the Ohmic contact resistance (R_C). However, because of the high doping level, cap layers become very sensitive to processing steps performed before and during gate recess etching. In this paper, the sensitivity of gate recess etching on a 20 nm highly-doped GaInAs cap layer (doped 7.3 × 10¹⁹ cm^-3) is studied with respect to Ohmic contact type (annealed/non-annealed), chip size, gate finger length, and etchant choice. The use of very high cap doping levels exacerbates device and process scaling challenges. For example, the recess finger length dependence complicates multi-project wafer runs which would simultaneously include narrow finger HEMTs used in digital ICs and longer finger HEMTs used in microwave analog circuits.

The RF harmonic distortion of coplanar waveguides (CPWs) fabricated on AlGaN/GaN HEMT heterostructures grown on both high-resistivity Si (GaN-on-Si) and semi-insulating SiC (GaN-on-SiC) substrates is reported for the first time. The loss performance and the nonlinear behavior of the CPW lines were experimentally characterized using both small- and large-signal measurements. From 100 MHz to 20 GHz, low loss (less than 0.3 dB/mm at 20 GHz) was achieved; the attenuation of CPW lines on the GaN-on-Si substrate is ~0.05 dB/mm higher than that of the GaN-on-SiC substrate. The harmonic distortion levels of the GaN-on-Si substrate and GaN-on-SiC were also evaluated experimentally; in contrast to the small-signal loss, more significant differences in second- and third-order nonlinearity, and thus intermodulation, are observed between Si and SiC substrates. Large-signal characterization of the GaN-on-Si substrate was carried out over temperature from 25 °C to 175 °C.  Due to increases in substrate conductivity with temperature, the harmonic distortion levels are found to increase significantly at temperatures above 75 °C.

We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

A single-layer optical filter made from thin film gallium phosphide (GaP) is envisioned and a fabrication flow is outlined, with current progress on process development reported. Ion-implantation is simulated and performed on bulk GaP with He⁺, followed by a field-assisted thermal bonding technique that simultaneously bonds a thin GaP film onto a borofloat glass substrate and removes the GaP substrate. The resulting thin films have consistent thickness, both within and between runs, and RMS surface roughness of < 10 nm. Dry-etch processes that further reduce the thin film material are characterized and designs for etching gratings into them are developed. This process is shown to be a reliable means of creating thin films of consistent thickness and smoothness in GaP, for the purpose of establishing visible wavelength filters for spectroscopic applications.

This work characterizes the effects of gate-length (L_G) scaling in a self-aligned gate (SAG) β-Ga₂O₃ MOSFET process. Additional performance gains are expected by extending the SAG process from large L_G to sub-micrometer dimensions.  This data incorporates L_G scaling down to 200 nm to improve device performance in Ga₂O₃ SAG MOSFETs using a stepper lithography process to define sub-micron gate lengths.

We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

NGMS reports the maturation of a novel GaN based 3D transistor with state of the art RF switch performance, named the SLCFET (Super Lattice Castellated Field Effect Transistor), with an RF switch FOM greater than 1.8 THz. The configured process has undergone reliability qualification for production.

This report describes the first demonstration of a 100nm T-gate for the Superlattice Castellation Field Effect Transistor (SLCFET) amplifier. The SLCFET amplifier device utilizes a superlattice of GaN/AlGaN channels, which enables a high charge density and low source resistance. A three-dimensional T-gate structure provides electrostatic control of the channels while maintaining high gain. Improvements to the T-gate process have allowed for the scaling of the gate down to 100nm while maintaining excellent gate control, with an on to off current ratio exceeding 10⁷. This gate scaling allows the device to reach F_T / F_MAX of 70/110 GHz with full passivation to maintain compatibility with the productionized SLCFET switch process.

To produce high performance AlGaN/GaN heterostructure field effect transistors for RF power applications, one of the critical control parameters of AlGaN/GaN system is the contact resistance (Rc) of the ohmic metal to AlGaN. In the present study, two important factors for the contact resistance, a Ti₃AlN interfacial layer and TiN islands were investigated using phase identification, and morphology as determined by Nano Beam Electron Diffraction (NBD) technique in transmission electron microscopy. Based on our study, both Ti₃AlN interfacial layer and TiN islands contribute to ohmic contact behavior in the system.

A low- Magnesium (Mg) out-diffusion normally off p-GaN gated AlGaN/GaN high-electron-mobility transistor (HEMT) was developed using a low-temperature laser activation technique. Conventionally, during the actual p-GaN layer activation procedure, Mg out-diffuses into the AlGaN barrier and GaN channel at high temperatures. In addition, the Al of the AlGaN barrier layer is injected into GaN to generate alloy scattering and to suppress current density. In this study, the GaN doped Mg layer (Mg:GaN)was activated using short-wavelength Nd:YAG pulse laser annealing, and a conventional thermal activation device was processed for comparison. The results demonstrated that the laser activation technique in p-GaN HEMT suppressed the Mg out-diffusion-induced leakage current and trapping effect and enhanced the current density and breakdown voltage. Therefore, using this novel technique, a high and active Mg concentration and a favorable doping confinement can be obtained in the p-GaN layer to realize a stable enhancement-mode operation.

In this study, a 50-nm Al_0.05Ga_0.95N back barrier (BB) layer was used in an AlGaN/GaN high-electron-mobility transistor between the two-dimensional electron gas channel and Fe-doped/C-doped buffer layers. This BB layer can reduce the channel layer. The BB layer is affected by doped carriers in the buffer layer and the conduction energy band between the channel and the buffer layers. The I_on/I_off ratio of the BB device was 3.43 × 10⁵ and the ratio for the device without BB was 1.91 × 10³. Lower leakage currents were obtained in the BB device because of the higher conduction energy band. The 0.25-μm gate length device with the BB exhibited a high current gain cutoff frequency of 26.9 GHz and power gain cutoff frequency of 54.7 GHz.

Metal–insulator–semiconductor p-type GaN high-electron-mobility transistor with an Al₂O₃/AlN deposited by atomic layer deposition was investigated. The selected insulator, AlN has been proven to have a good interface with GaN. A traditional p-GaN device without an Al₂O₃/AlN layer was processed for comparison. Due to the Al₂O₃/AlN layer, the gate leakage was lower, and the threshold voltage was higher, at 4.7 V. Additionally, excellent turn-on voltage was obtained. Furthermore, low current degradation and smaller V_TH shift at high temperatures was also observed. Hence, growing a good-quality Al₂O₃/AlN layer can achieve an enhancement-mode operation with superior stability and high gate swing region.

In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al_0.08GaN) of the B.B. more strongly affected the device’ I_on/I_off ratio. It exhibited a low leakage current and high I_on/I_off ratio of approximately 10⁶. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic R_ON. The current gain cut-off frequency (f_T) and maximum stable gain cut-off frequency (f_max) were 5.2 GHz and 10.5 GHz, respectively, for the Al_0.08GaN B.B. device.

Metal–insulator–semiconductor p-type GaN high-electron-mobility transistor with an Al₂O₃/AlN deposited by atomic layer deposition was investigated. The selected insulator, AlN has been proven to have a good interface with GaN. A traditional p-GaN device without an Al₂O₃/AlN layer was processed for comparison. Due to the Al₂O₃/AlN layer, the gate leakage was lower, and the threshold voltage was higher, at 4.7 V. Additionally, excellent turn-on voltage was obtained. Furthermore, low current degradation and smaller V_TH shift at high temperatures was also observed. Hence, growing a good-quality Al₂O₃/AlN layer can achieve an enhancement-mode operation with superior stability and high gate swing region.

In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al_0.08GaN) of the B.B. more strongly affected the device’ I_on/I_off ratio. It exhibited a low leakage current and high I_on/I_off ratio of approximately 10⁶. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic R_ON. The current gain cut-off frequency (f_T) and maximum stable gain cut-off frequency (f_max) were 5.2 GHz and 10.5 GHz, respectively, for the Al_0.08GaN B.B. device.

Metal–insulator–semiconductor p-type GaN high-electron-mobility transistor with an Al₂O₃/AlN deposited by atomic layer deposition was investigated. The selected insulator, AlN has been proven to have a good interface with GaN. A traditional p-GaN device without an Al₂O₃/AlN layer was processed for comparison. Due to the Al₂O₃/AlN layer, the gate leakage was lower, and the threshold voltage was higher, at 4.7 V. Additionally, excellent turn-on voltage was obtained. Furthermore, low current degradation and smaller V_TH shift at high temperatures was also observed. Hence, growing a good-quality Al₂O₃/AlN layer can achieve an enhancement-mode operation with superior stability and high gate swing region.

A low- Magnesium (Mg) out-diffusion normally off p-GaN gated AlGaN/GaN high-electron-mobility transistor (HEMT) was developed using a low-temperature laser activation technique. Conventionally, during the actual p-GaN layer activation procedure, Mg out-diffuses into the AlGaN barrier and GaN channel at high temperatures. In addition, the Al of the AlGaN barrier layer is injected into GaN to generate alloy scattering and to suppress current density. In this study, the GaN doped Mg layer (Mg:GaN)was activated using short-wavelength Nd:YAG pulse laser annealing, and a conventional thermal activation device was processed for comparison. The results demonstrated that the laser activation technique in p-GaN HEMT suppressed the Mg out-diffusion-induced leakage current and trapping effect and enhanced the current density and breakdown voltage. Therefore, using this novel technique, a high and active Mg concentration and a favorable doping confinement can be obtained in the p-GaN layer to realize a stable enhancement-mode operation.

To produce high performance AlGaN/GaN heterostructure field effect transistors for RF power applications, one of the critical control parameters of AlGaN/GaN system is the contact resistance (Rc) of the ohmic metal to AlGaN. In the present study, two important factors for the contact resistance, a Ti₃AlN interfacial layer and TiN islands were investigated using phase identification, and morphology as determined by Nano Beam Electron Diffraction (NBD) technique in transmission electron microscopy. Based on our study, both Ti₃AlN interfacial layer and TiN islands contribute to ohmic contact behavior in the system.

Typical n-type ohmic contact formation for GaN material systems requires high-temperature thermal processes. The high-temperature process often leads to a rough surface after the annealing step. Low-annealing-ohmic contact is advantageous to prevent undesired surface roughening on the metal stack during this thermal process.  We report an approach to achieve low contact resistance on n-type GaN layers using a nitrogen plasma and a conventional Ti/Al-based metal stacks.  We observed an as-deposit ohmic contact behavior on the n-type contact with a specific contact resistance (r_c,sp) in the mid-E-6 Ω∙cm² range.  The r_c,sp was further reduced to  6.8E-7 Ω∙cm² after an annealing step at 600 ^oC.

This work focuses on evaluating and demonstrating channeled p-type and n-type implantations in silicon carbide in a repeatable mass-production environment. Range increase of about 3X is observed using channeled conditions as opposed to normal incident conditions for both Aluminum and Phosphorous. The various advantages enabled by this technology for advanced device designs are highlighted. Super-junction devices targeting the same voltage range can be fabricated using 1 or 2 lesser epitaxial regrowth layers.

The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

This work describes an on-going effort to develop and mature a 140 nm GaN MMIC technology with a focus on efficient power amplification at frequencies ranging from DC to 50 GHz and a 90 nm technology targeted towards V- and W-band applications, and then release the technologies within a foundry process that is open to the DoD community.

In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al_0.08GaN) of the B.B. more strongly affected the device’ I_on/I_off ratio. It exhibited a low leakage current and high I_on/I_off ratio of approximately 10⁶. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic R_ON. The current gain cut-off frequency (f_T) and maximum stable gain cut-off frequency (f_max) were 5.2 GHz and 10.5 GHz, respectively, for the Al_0.08GaN B.B. device.

This work describes an on-going effort to develop and mature a 140 nm GaN MMIC technology with a focus on efficient power amplification at frequencies ranging from DC to 50 GHz and a 90 nm technology targeted towards V- and W-band applications, and then release the technologies within a foundry process that is open to the DoD community.

We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

A single-layer optical filter made from thin film gallium phosphide (GaP) is envisioned and a fabrication flow is outlined, with current progress on process development reported. Ion-implantation is simulated and performed on bulk GaP with He⁺, followed by a field-assisted thermal bonding technique that simultaneously bonds a thin GaP film onto a borofloat glass substrate and removes the GaP substrate. The resulting thin films have consistent thickness, both within and between runs, and RMS surface roughness of < 10 nm. Dry-etch processes that further reduce the thin film material are characterized and designs for etching gratings into them are developed. This process is shown to be a reliable means of creating thin films of consistent thickness and smoothness in GaP, for the purpose of establishing visible wavelength filters for spectroscopic applications.

In this work we compare non-contact charge-voltage imaging and UV-photoluminescence (UV-PL) imaging of yield killer defects in epitaxial 4H-SiC wafers.  Two significant findings are based on macro- and micro-scale imaging, respectively.  1- Whole wafer images demonstrate that only a fraction of the UV-PL defects in triangular, downfall and carrot categories are electrically active. 2- Micro-scale images reveal similarities and differences between PL and electrical defect images.  Presented for the first time, micrometer resolution leakage patterns within triangular defects are consistent with the microstructure modeling in reference 1. The results imply that the depletion layer leakage within killer defects corresponds to exposed 3C-SiC polytypes. This leakage may be a consequence of the lower 2.2eV energy gap of 3C-SiC compared to 3.3eV in 4H-SiC.

Typical n-type ohmic contact formation for GaN material systems requires high-temperature thermal processes. The high-temperature process often leads to a rough surface after the annealing step. Low-annealing-ohmic contact is advantageous to prevent undesired surface roughening on the metal stack during this thermal process.  We report an approach to achieve low contact resistance on n-type GaN layers using a nitrogen plasma and a conventional Ti/Al-based metal stacks.  We observed an as-deposit ohmic contact behavior on the n-type contact with a specific contact resistance (r_c,sp) in the mid-E-6 Ω∙cm² range.  The r_c,sp was further reduced to  6.8E-7 Ω∙cm² after an annealing step at 600 ^oC.

Bulk induced dynamic R_ON in GaN-on-Si HEMTs is a serious performance limiting instability which remains a problem even in some commercially available power switching devices. Its origin is now reasonably well understood, however until now it has not been possible to simulate it using a realistic epitaxial stack. For the first time we successfully simulate the controlled suppression of bulk dynamic R_ON by adding a specific model for leakage along threading dislocations. This was undertaken using a commercially available standard TCAD simulator, allowing realistic device optimization in an advanced GaN HEMT design flow.

A single-layer optical filter made from thin film gallium phosphide (GaP) is envisioned and a fabrication flow is outlined, with current progress on process development reported. Ion-implantation is simulated and performed on bulk GaP with He⁺, followed by a field-assisted thermal bonding technique that simultaneously bonds a thin GaP film onto a borofloat glass substrate and removes the GaP substrate. The resulting thin films have consistent thickness, both within and between runs, and RMS surface roughness of < 10 nm. Dry-etch processes that further reduce the thin film material are characterized and designs for etching gratings into them are developed. This process is shown to be a reliable means of creating thin films of consistent thickness and smoothness in GaP, for the purpose of establishing visible wavelength filters for spectroscopic applications.

The transistor-injected quantum cascade laser (TI-QCL) is a novel design for a mid-wave infrared (MWIR) laser that seeks to overcome some of the primary limitations of standard quantum cascade lasers (QCLs). By growing the active cascade region within the base-collector junction of an n-p-n heterojunction bipolar transistor (HBT), independent control of the injection current and active region bias is achievable through the emitter current and base-collector reverse bias respectively. The active region bias is important to properly align the lasing states and to control the lasing wavelength. Physical design limitations of the TI-QCL and their effects on the fabrication process of samples is presented. In order to characterize device performance and validate fabrication improvements, InP-based device samples designed for λ = 7.3 µm emission are fabricated. Preliminary characterization results are shown in the form of diode measurements to validate the HBT electrical operation of the TI-QCL which is necessary to realize the optical benefits of the device.

In order to meet the forecast growing demand of n⁺ SiC material, wafer suppliers will need to implement new metrology techniques to allow the detection of crystalline defects and ensure the quality of their materials. Incumbent techniques such as KOH etching have been used for many years but remain very costly as the wafers cannot be processed further. Alternative techniques such as X-ray Diffraction Imaging (X-ray Topography) can be used to detect crystalline defects non-destructively but studies have been limited to synchrotron radiation which cannot be used as an in-line characterization. In this paper, Bruker have used novel equipment (Sensus-CS) to study the correlation between laboratory X-ray Diffraction Imaging and KOH etching performed at the University of Warwick.

This work focuses on evaluating and demonstrating channeled p-type and n-type implantations in silicon carbide in a repeatable mass-production environment. Range increase of about 3X is observed using channeled conditions as opposed to normal incident conditions for both Aluminum and Phosphorous. The various advantages enabled by this technology for advanced device designs are highlighted. Super-junction devices targeting the same voltage range can be fabricated using 1 or 2 lesser epitaxial regrowth layers.

Plasma dicing of silicon wafers is beginning to move from pilot scale into mainstream production. Attention is now focusing on other market sectors which may benefit from a similar dicing approach.  The fragility of GaAs wafers leads to issues (such as wafer breakages, damage to die edges) during conventional wafer saw dicing. Although LASER techniques have been developed, they also have their own drawbacks – specifically sidewall quality.  A systematic investigation of the current capabilities of plasma dicing of GaAs substrates has been performed, developing technology which is both practical and economically viable. Preliminary results show smooth vertical sidewalls of trenches suitable for dicing thinned GaAs substrates at etch rates up to 23μm min^-1.

Plasma dicing of silicon wafers is beginning to move from pilot scale into mainstream production. Attention is now focusing on other market sectors which may benefit from a similar dicing approach.  The fragility of GaAs wafers leads to issues (such as wafer breakages, damage to die edges) during conventional wafer saw dicing. Although LASER techniques have been developed, they also have their own drawbacks – specifically sidewall quality.  A systematic investigation of the current capabilities of plasma dicing of GaAs substrates has been performed, developing technology which is both practical and economically viable. Preliminary results show smooth vertical sidewalls of trenches suitable for dicing thinned GaAs substrates at etch rates up to 23μm min^-1.

GaN power ICs on engineered substrates of Qromis substrate technology (QST^®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm² leakage current at 150 °C. The fabricated 36 mm power HEMTs with L_GD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

The etching of uniform, repeatable GaAs/AlGaAs mesas is an important step in manufacturing VCSELs. This paper presents a high uniformity, low foot etching of mesa structures on 6” wafers. The improved uniformity permits the use of production-friendly optical endpoint techniques which can be used to stop on a specific layer in the VCSEL structure.

Typical n-type ohmic contact formation for GaN material systems requires high-temperature thermal processes. The high-temperature process often leads to a rough surface after the annealing step. Low-annealing-ohmic contact is advantageous to prevent undesired surface roughening on the metal stack during this thermal process.  We report an approach to achieve low contact resistance on n-type GaN layers using a nitrogen plasma and a conventional Ti/Al-based metal stacks.  We observed an as-deposit ohmic contact behavior on the n-type contact with a specific contact resistance (r_c,sp) in the mid-E-6 Ω∙cm² range.  The r_c,sp was further reduced to  6.8E-7 Ω∙cm² after an annealing step at 600 ^oC.

We have developed a family of opto-plasmonic devices (OPDs) for next generation Tera-bits-per-second (Tbps) tele/data communication infrastructure. Particularly, a top illuminated optical detector is produced as an essential part of the value chain in PIC. This solves a bottleneck in high-speed PIC that currently use Germanium-based photodetectors. Specifically, a photodetector is demonstrated that operates at a 6x higher bandwidth and at 10-20x lower optical power conditions, compared to a commonly used 40-GHz pin device. These provide value for optics engineers to design: i) an optical receiver module with a %75 enhancement in reliability, and ii) an optical link with 10x extension in length.

We have developed a family of opto-plasmonic devices (OPDs) for next generation Tera-bits-per-second (Tbps) tele/data communication infrastructure. Particularly, a top illuminated optical detector is produced as an essential part of the value chain in PIC. This solves a bottleneck in high-speed PIC that currently use Germanium-based photodetectors. Specifically, a photodetector is demonstrated that operates at a 6x higher bandwidth and at 10-20x lower optical power conditions, compared to a commonly used 40-GHz pin device. These provide value for optics engineers to design: i) an optical receiver module with a %75 enhancement in reliability, and ii) an optical link with 10x extension in length.

This work describes an on-going effort to develop and mature a 140 nm GaN MMIC technology with a focus on efficient power amplification at frequencies ranging from DC to 50 GHz and a 90 nm technology targeted towards V- and W-band applications, and then release the technologies within a foundry process that is open to the DoD community.

Wet chemical lift off in N-Methyl-2-pyrrolidone (NMP) is widely used in GaN HEMT Front End manufacturing.  In case of a Ti-Al-Ni-Au based metal stack for ohmic contacts, the quality of the lift-off process is much depending on the water content in the solvent NMP. In this paper, it will be shown that the metal stack can be attacked during lift off in NMP with too high water content. Additionally, environmental impacts on the hygroscopy of NMP are investigated in order to keep moisture below a certain level and avoid optical defects on ohmic contacts after lift off.

The high growth of the EV/HEV market impacted significantly the wide bandgap semiconductor industry, creating new opportunities and a competition between SiC and GaN in many applications such as on-board chargers, DC-DC converters and main inverters. This paper provides an overview of SiC and GaN device technology, including Yole Développement’s understanding of the market’s current dynamics and future evolution of wide band gap materials compared to mainstream Silicon power electronics market.

The paper presents the market overview of different compound semiconductor such as GaN, GaAs, and InP impacted by the deployment of 5G in wireless infrastructure. The value chain from wafer and epitaxy to device level is covered, as well as technology and market trends and Yole’s forecast for the coming years.

Schottky devices play an important role in modern electronics. The forward biased current-voltage characteristics of such devices are linear on a semi-logarithm scale at intermediate bias voltages. However, the curve deviates from linearity at higher voltage primarily due to series resistance. The applied forward voltage on the device is equal to the sum of the voltage drops across the (1) junction, (2) series resistance, (3) depletion layer and (4) any parasitic resistive layer between the Schottky metal and the semiconductor. Therefore, the interface between the metal and the semiconductor plays an important role in determining the critical parameters of Schottky devices. In this investigation a controlled delay was introduced between the pre-metal clean and Schottky metal deposition steps of the fabrication process to study the effects of naturally grown oxide on the forward characteristics of the Schottky devices.  The results of the investigation indicate such delays cause significant increases in series resistance and ideality factor, as well as a decrease in barrier height.

This work characterizes the effects of gate-length (L_G) scaling in a self-aligned gate (SAG) β-Ga₂O₃ MOSFET process. Additional performance gains are expected by extending the SAG process from large L_G to sub-micrometer dimensions.  This data incorporates L_G scaling down to 200 nm to improve device performance in Ga₂O₃ SAG MOSFETs using a stepper lithography process to define sub-micron gate lengths.

This report describes the first demonstration of a 100nm T-gate for the Superlattice Castellation Field Effect Transistor (SLCFET) amplifier. The SLCFET amplifier device utilizes a superlattice of GaN/AlGaN channels, which enables a high charge density and low source resistance. A three-dimensional T-gate structure provides electrostatic control of the channels while maintaining high gain. Improvements to the T-gate process have allowed for the scaling of the gate down to 100nm while maintaining excellent gate control, with an on to off current ratio exceeding 10⁷. This gate scaling allows the device to reach F_T / F_MAX of 70/110 GHz with full passivation to maintain compatibility with the productionized SLCFET switch process.

Major cost gaps were identified from a benchmark (BM) study for a Semiconductor fab. The study triggered deep-dive assessments of both maintenance practices and supply chain business processes. Those assessments uncovered significant improvement opportunities. In this paper, we discuss the approach used to identify and quantify those opportunities, and share important results and observations with the Compound Semiconductor (CS) manufacturing community.

Typical n-type ohmic contact formation for GaN material systems requires high-temperature thermal processes. The high-temperature process often leads to a rough surface after the annealing step. Low-annealing-ohmic contact is advantageous to prevent undesired surface roughening on the metal stack during this thermal process.  We report an approach to achieve low contact resistance on n-type GaN layers using a nitrogen plasma and a conventional Ti/Al-based metal stacks.  We observed an as-deposit ohmic contact behavior on the n-type contact with a specific contact resistance (r_c,sp) in the mid-E-6 Ω∙cm² range.  The r_c,sp was further reduced to  6.8E-7 Ω∙cm² after an annealing step at 600 ^oC.

GaN is a promising material for more efficient high frequency and high voltage power switching. However, GaN still is not the common material for power electronics due to immature substrate, homoepitaxial growth, and processing technology. Electroluminescence is a promising method to predict failure points due to high field stress, which can assist in the separation of inherent defects stemming from substrate quality, and from process-induced defects as well as identify problems related to proper edge termination design. In this work, we compare the Electroluminescence signatures of devices on inhomogeneous substrates to DC I-V behavior to demonstrate the utility of the technique for process monitoring.

It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

We have demonstrated the vertical GaN planar-gate MOSFETs fabricated by an ion implantation process.  The fabricated GaN vertical MOSFET shows a specific on-resistance of 2.78 mΩ cm² and a breakdown voltage of 1200 V, by applying a Mg and N sequential implantation to improve the breakdown voltage of the pn-junction and the control of the MOS channel characteristics on the p-type ion implanted layer.  Consequently, the vertical GaN planar-gate MOSFETs with high breakdown voltage and low on-resistance could be realized by ion implantation process.  On the other hand, there are still many challenges for realizing practical GaN vertical MOSFETs, so continuous development is necessary.

Wet chemical lift off in N-Methyl-2-pyrrolidone (NMP) is widely used in GaN HEMT Front End manufacturing.  In case of a Ti-Al-Ni-Au based metal stack for ohmic contacts, the quality of the lift-off process is much depending on the water content in the solvent NMP. In this paper, it will be shown that the metal stack can be attacked during lift off in NMP with too high water content. Additionally, environmental impacts on the hygroscopy of NMP are investigated in order to keep moisture below a certain level and avoid optical defects on ohmic contacts after lift off.

A die sort (DS) yield loss forming a ‘starburst’ pattern in a wafermap was observed in a pHEMT technology manufactured by Qorvo. Typical data analysis performed by yield engineers was unable to correlate the failure root cause to a specific process step. To help drive to root cause, Bistel was consulted on the use of eDataLyzer (eDL) software.

This paper will describe the ‘starburst’ DS yield loss pattern in details, followed by the application of Bistel’s eDL software combined with process tool Fault Detection and Correlation (FDC), and end with the validation of the failure mode.

NiCr is one of the most commonly used resistive materials for fabricating precision thin film resistors due to its wide range of resistivity, low temperature coefficient of resistivity (TCR), and high stability of electrical properties. NiCr thin film resistors are usually manufactured by evaporation or sputtering. It is well known that thermal evaporation of NiCr from a finite mass of molten alloy causes a film composition change away from the composition of the source, as well as film composition changes from run to run. Some electrical properties of NiCr thin film resistors strongly depend on the film microstructure (i.e. Ni:Cr ratio) in addition to its spatial geometry (film thickness) and the deposition parameters in the evaporator. As a result, while film thickness and deposition parameters are well controlled, often time resistivity of evaporated NiCr thin film resistors goes out of spec. Therefore, in this paper we are investigating the possibility of replacing the evaporated NiCr thin films with the sputtered NiCr thin films as resistors. Here, we present a comprehensive study of NiCr thin film resistors developed using DC sputtering system and discuss the effects of sputtering process parameters and substrate conditions on film microstructure, TCR and electrical properties.

Plasma dicing of silicon wafers is beginning to move from pilot scale into mainstream production. Attention is now focusing on other market sectors which may benefit from a similar dicing approach.  The fragility of GaAs wafers leads to issues (such as wafer breakages, damage to die edges) during conventional wafer saw dicing. Although LASER techniques have been developed, they also have their own drawbacks – specifically sidewall quality.  A systematic investigation of the current capabilities of plasma dicing of GaAs substrates has been performed, developing technology which is both practical and economically viable. Preliminary results show smooth vertical sidewalls of trenches suitable for dicing thinned GaAs substrates at etch rates up to 23μm min^-1.

NiCr is one of the most commonly used resistive materials for fabricating precision thin film resistors due to its wide range of resistivity, low temperature coefficient of resistivity (TCR), and high stability of electrical properties. NiCr thin film resistors are usually manufactured by evaporation or sputtering. It is well known that thermal evaporation of NiCr from a finite mass of molten alloy causes a film composition change away from the composition of the source, as well as film composition changes from run to run. Some electrical properties of NiCr thin film resistors strongly depend on the film microstructure (i.e. Ni:Cr ratio) in addition to its spatial geometry (film thickness) and the deposition parameters in the evaporator. As a result, while film thickness and deposition parameters are well controlled, often time resistivity of evaporated NiCr thin film resistors goes out of spec. Therefore, in this paper we are investigating the possibility of replacing the evaporated NiCr thin films with the sputtered NiCr thin films as resistors. Here, we present a comprehensive study of NiCr thin film resistors developed using DC sputtering system and discuss the effects of sputtering process parameters and substrate conditions on film microstructure, TCR and electrical properties.

GaN power ICs on engineered substrates of Qromis substrate technology (QST^®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm² leakage current at 150 °C. The fabricated 36 mm power HEMTs with L_GD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

A nanoindentation induced blistering method has been used to extract the GaN/diamond interfacial toughness (adhesion energy) from four types of GaN-on-diamond samples with varying SiN_x interlayer thicknesses. The mode I energy release rate (G_IC) was quantified and is presented. Additionally, transient thermoreflectance has been used to measure the thermal boundary resistance (TBR) between the GaN and the diamond substrate. It was found that a thin SiN_x interlayer resulted in a lower TBR (15 m² K GW^-1) whilst maintaining a reasonable interfacial toughness (1.4±0.5 J m^-2). For interlayers of a similar thickness, samples with a high interfacial toughness and high residual stresses in the GaN had a smaller TBR. This indicates that the intrinsic interfacial characteristics that enhanced the interfacial toughness could be beneficial in improving the TBR.

This report describes the first demonstration of a 100nm T-gate for the Superlattice Castellation Field Effect Transistor (SLCFET) amplifier. The SLCFET amplifier device utilizes a superlattice of GaN/AlGaN channels, which enables a high charge density and low source resistance. A three-dimensional T-gate structure provides electrostatic control of the channels while maintaining high gain. Improvements to the T-gate process have allowed for the scaling of the gate down to 100nm while maintaining excellent gate control, with an on to off current ratio exceeding 10⁷. This gate scaling allows the device to reach F_T / F_MAX of 70/110 GHz with full passivation to maintain compatibility with the productionized SLCFET switch process.

The RF harmonic distortion of coplanar waveguides (CPWs) fabricated on AlGaN/GaN HEMT heterostructures grown on both high-resistivity Si (GaN-on-Si) and semi-insulating SiC (GaN-on-SiC) substrates is reported for the first time. The loss performance and the nonlinear behavior of the CPW lines were experimentally characterized using both small- and large-signal measurements. From 100 MHz to 20 GHz, low loss (less than 0.3 dB/mm at 20 GHz) was achieved; the attenuation of CPW lines on the GaN-on-Si substrate is ~0.05 dB/mm higher than that of the GaN-on-SiC substrate. The harmonic distortion levels of the GaN-on-Si substrate and GaN-on-SiC were also evaluated experimentally; in contrast to the small-signal loss, more significant differences in second- and third-order nonlinearity, and thus intermodulation, are observed between Si and SiC substrates. Large-signal characterization of the GaN-on-Si substrate was carried out over temperature from 25 °C to 175 °C.  Due to increases in substrate conductivity with temperature, the harmonic distortion levels are found to increase significantly at temperatures above 75 °C.

Fabrication techniques and experimental data are presented for 850 nm GaAs P-i-N photodiodes designed for 50 Gb/s optical links. Optimizations in the device structure and the selective dry etching process reduce dark current below 1pA. Responsivity is shown to be comparable to commercial devices with similar dimensions. And microwave measurement shows a highest bandwidth of above 30 GHz, indicating potential for 60 Gb/s operation. Data rate testing is performed with a VCSEL up to 50 Gb/s, showing clear eye diagrams.

Wet-etching issues in type-II DHBT process fabricated by standard triple-mesa wet-etching have been identified and reported in this paper. For comparison, devices fabricated by hybrid-etching with incorporation of inductively-coupled-plasma (ICP) are also present. With better uniformity and yield, hybrid-etching process can potentially lead to a more reliable and reproducible process for 5G power amplifier application.

The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

A nanoindentation induced blistering method has been used to extract the GaN/diamond interfacial toughness (adhesion energy) from four types of GaN-on-diamond samples with varying SiN_x interlayer thicknesses. The mode I energy release rate (G_IC) was quantified and is presented. Additionally, transient thermoreflectance has been used to measure the thermal boundary resistance (TBR) between the GaN and the diamond substrate. It was found that a thin SiN_x interlayer resulted in a lower TBR (15 m² K GW^-1) whilst maintaining a reasonable interfacial toughness (1.4±0.5 J m^-2). For interlayers of a similar thickness, samples with a high interfacial toughness and high residual stresses in the GaN had a smaller TBR. This indicates that the intrinsic interfacial characteristics that enhanced the interfacial toughness could be beneficial in improving the TBR.

Schottky devices play an important role in modern electronics. The forward biased current-voltage characteristics of such devices are linear on a semi-logarithm scale at intermediate bias voltages. However, the curve deviates from linearity at higher voltage primarily due to series resistance. The applied forward voltage on the device is equal to the sum of the voltage drops across the (1) junction, (2) series resistance, (3) depletion layer and (4) any parasitic resistive layer between the Schottky metal and the semiconductor. Therefore, the interface between the metal and the semiconductor plays an important role in determining the critical parameters of Schottky devices. In this investigation a controlled delay was introduced between the pre-metal clean and Schottky metal deposition steps of the fabrication process to study the effects of naturally grown oxide on the forward characteristics of the Schottky devices.  The results of the investigation indicate such delays cause significant increases in series resistance and ideality factor, as well as a decrease in barrier height.

We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

A nanoindentation induced blistering method has been used to extract the GaN/diamond interfacial toughness (adhesion energy) from four types of GaN-on-diamond samples with varying SiN_x interlayer thicknesses. The mode I energy release rate (G_IC) was quantified and is presented. Additionally, transient thermoreflectance has been used to measure the thermal boundary resistance (TBR) between the GaN and the diamond substrate. It was found that a thin SiN_x interlayer resulted in a lower TBR (15 m² K GW^-1) whilst maintaining a reasonable interfacial toughness (1.4±0.5 J m^-2). For interlayers of a similar thickness, samples with a high interfacial toughness and high residual stresses in the GaN had a smaller TBR. This indicates that the intrinsic interfacial characteristics that enhanced the interfacial toughness could be beneficial in improving the TBR.

This report describes the first demonstration of a 100nm T-gate for the Superlattice Castellation Field Effect Transistor (SLCFET) amplifier. The SLCFET amplifier device utilizes a superlattice of GaN/AlGaN channels, which enables a high charge density and low source resistance. A three-dimensional T-gate structure provides electrostatic control of the channels while maintaining high gain. Improvements to the T-gate process have allowed for the scaling of the gate down to 100nm while maintaining excellent gate control, with an on to off current ratio exceeding 10⁷. This gate scaling allows the device to reach F_T / F_MAX of 70/110 GHz with full passivation to maintain compatibility with the productionized SLCFET switch process.

Photoelectrochemical (PEC) etching is a promising technology for fabricating GaN devices with low damage. In the simple contactless PEC (CL–PEC) etching process that includes K₂S₂O₈ in the electrolyte as an oxidizing agent, a sample is dipped into the electrolyte under UV irradiation. In this study, we applied CL–PEC to the gate-recess process of GaN HEMTs on an SiC substrate. The etching depth of the recess showed considerable reproducibility by the self-termination feature, and the residual AlGaN layer thickness was approximately 5 nm. The Schottky gate HEMTs with a recessed structure showed the normally off characteristics, and the V_th value was +0.4 V with a standard deviation of ±3.8 mV.

We have demonstrated the vertical GaN planar-gate MOSFETs fabricated by an ion implantation process.  The fabricated GaN vertical MOSFET shows a specific on-resistance of 2.78 mΩ cm² and a breakdown voltage of 1200 V, by applying a Mg and N sequential implantation to improve the breakdown voltage of the pn-junction and the control of the MOS channel characteristics on the p-type ion implanted layer.  Consequently, the vertical GaN planar-gate MOSFETs with high breakdown voltage and low on-resistance could be realized by ion implantation process.  On the other hand, there are still many challenges for realizing practical GaN vertical MOSFETs, so continuous development is necessary.

GaN is a promising material for more efficient high frequency and high voltage power switching. However, GaN still is not the common material for power electronics due to immature substrate, homoepitaxial growth, and processing technology. Electroluminescence is a promising method to predict failure points due to high field stress, which can assist in the separation of inherent defects stemming from substrate quality, and from process-induced defects as well as identify problems related to proper edge termination design. In this work, we compare the Electroluminescence signatures of devices on inhomogeneous substrates to DC I-V behavior to demonstrate the utility of the technique for process monitoring.

The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

In order to meet the forecast growing demand of n⁺ SiC material, wafer suppliers will need to implement new metrology techniques to allow the detection of crystalline defects and ensure the quality of their materials. Incumbent techniques such as KOH etching have been used for many years but remain very costly as the wafers cannot be processed further. Alternative techniques such as X-ray Diffraction Imaging (X-ray Topography) can be used to detect crystalline defects non-destructively but studies have been limited to synchrotron radiation which cannot be used as an in-line characterization. In this paper, Bruker have used novel equipment (Sensus-CS) to study the correlation between laboratory X-ray Diffraction Imaging and KOH etching performed at the University of Warwick.

A die sort (DS) yield loss forming a ‘starburst’ pattern in a wafermap was observed in a pHEMT technology manufactured by Qorvo. Typical data analysis performed by yield engineers was unable to correlate the failure root cause to a specific process step. To help drive to root cause, Bistel was consulted on the use of eDataLyzer (eDL) software.

This paper will describe the ‘starburst’ DS yield loss pattern in details, followed by the application of Bistel’s eDL software combined with process tool Fault Detection and Correlation (FDC), and end with the validation of the failure mode.

A single-layer optical filter made from thin film gallium phosphide (GaP) is envisioned and a fabrication flow is outlined, with current progress on process development reported. Ion-implantation is simulated and performed on bulk GaP with He⁺, followed by a field-assisted thermal bonding technique that simultaneously bonds a thin GaP film onto a borofloat glass substrate and removes the GaP substrate. The resulting thin films have consistent thickness, both within and between runs, and RMS surface roughness of < 10 nm. Dry-etch processes that further reduce the thin film material are characterized and designs for etching gratings into them are developed. This process is shown to be a reliable means of creating thin films of consistent thickness and smoothness in GaP, for the purpose of establishing visible wavelength filters for spectroscopic applications.

In this work we present a systematic study on the conduction properties in vertical GaN trench MISFETs grown and manufactured on different free standing GaN substrates. It is shown that devices manufactured on ammonothermal substrates have superior conduction current density higher than 4 kA/cm², specific on‑state resistance as low as 1.1 ± 0.1 mWcm² and channel sheet resistance of 19.6 ± 0.9 Wmm. It is further shown that scaling these devices to large gate periphery is not limited by current spreading in the drift region, low channel mobility or by self‑heating. The conduction properties of devices manufactured on ammonothermal GaN substrates are found to be the most suitable for pulsed laser driving applications.

GaN power ICs on engineered substrates of Qromis substrate technology (QST^®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm² leakage current at 150 °C. The fabricated 36 mm power HEMTs with L_GD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

Pad conditioning is critical to maintaining the required process stability and performance in semiconductor CMP. As the process and performance requirements for substrate polishing in the compound semiconductor industry become more stringent, we believe there are significant opportunities for improvement via more extensive adoption of optimized pad conditioning protocols. In this paper we will review the pertinent state of the art in semiconductor CMP and propose some specific target areas for adoption in compound semiconductor substrate polishing.

We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

This work characterizes the effects of gate-length (L_G) scaling in a self-aligned gate (SAG) β-Ga₂O₃ MOSFET process. Additional performance gains are expected by extending the SAG process from large L_G to sub-micrometer dimensions.  This data incorporates L_G scaling down to 200 nm to improve device performance in Ga₂O₃ SAG MOSFETs using a stepper lithography process to define sub-micron gate lengths.

We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

Determination of reliability performance over time requires an accurate understanding of device junction temperature, not only in customer use condition, but also during production test and burn-in. Through carefully designed and executed LIV (L=Light, I=current, V=Voltage) measurements and a modeling framework where optical power, thermal and electrical device parameters are interrelated, the laser diode junction temperature, as confirmed by wavelength shift measurements, is obtained via regression of a non-linear self-consistent equation.  Modeled parameters include both threshold current and slope efficiency junction linear temperature dependence coefficients/constants, as well as a thermal impedance factor.

Previous studies have shown the importance of selecting the correct photoresist, metallization method, resist remover, and tool to achieve a successful lift-off^[1].  Improper selection of just one of the four can result in insufficient lift-off due to conformal metal coating of the photoresist, greater number of defects, lower throughput and a higher cost of ownership.  Feature sizes of 50 µm down to 0.5 µm were previously demonstrated and this paper will focus on feature sizes under 0.5 µm.  These size features are gaining more traction in metal lift-off processes for RF and power applications that require smaller features for improved performance.

In this work we compare non-contact charge-voltage imaging and UV-photoluminescence (UV-PL) imaging of yield killer defects in epitaxial 4H-SiC wafers.  Two significant findings are based on macro- and micro-scale imaging, respectively.  1- Whole wafer images demonstrate that only a fraction of the UV-PL defects in triangular, downfall and carrot categories are electrically active. 2- Micro-scale images reveal similarities and differences between PL and electrical defect images.  Presented for the first time, micrometer resolution leakage patterns within triangular defects are consistent with the microstructure modeling in reference 1. The results imply that the depletion layer leakage within killer defects corresponds to exposed 3C-SiC polytypes. This leakage may be a consequence of the lower 2.2eV energy gap of 3C-SiC compared to 3.3eV in 4H-SiC.

GaN power ICs on engineered substrates of Qromis substrate technology (QST^®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm² leakage current at 150 °C. The fabricated 36 mm power HEMTs with L_GD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

GaN power ICs on engineered substrates of Qromis substrate technology (QST^®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm² leakage current at 150 °C. The fabricated 36 mm power HEMTs with L_GD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

With expanding applications and growing performance requirements in Power, RF and Optoelectronics markets, leading device manufacturers are looking for new ways to characterize yield-limiting defects that will help them achieve faster development and ramp times, higher product yields and lower device costs. Full-surface, high sensitivity defect inspection and accurate process control feedback has enabled the industry to improve substrate quality as well as to optimize the yields on epitaxy growth processes.
     As device manufacturers continue to push the boundaries of process designs, the requirements for defect inspection and overall yield management become increasingly more stringent and critical. The Candela unified surface and photoluminescence (PL) defect inspection platform enables high sensitivity inspection and defect classification at production throughputs of a wide range of critical defects (e.g. micro scratches, stacking faults, basal plane dislocations) and effectively separates front-surface defects and buried defects on transparent SiC substrates and epitaxial material. In addition, automated defect classification capabilities reduce the time required to identify, source and correct various yield-limiting defects such as carrots, triangles, sub-micron pits and others.
     The process of growing III-V epitaxy has unique challenges. The large mismatch in the lattice constant and the thermal expansion coefficient between epitaxy layer and substrate causes high lattice stress which leads to cracking on and through the epitaxy layer, making parts of the wafer unsuitable for device production. This cracking can be minimized by using a suitable buffer layer and optimizing the epitaxy reactor conditions. Improper epitaxy reactor conditions may also cause other device reliability killer defects such as micropits, craters, epi droplets and/or bumps.
     This study discusses how multiple complementary techniques such as scatterometry, reflectometry, ellipsometry and photoluminescence could be used together for simultaneous detection and classification of multiple critical defects on compound semiconductor wafers. We demonstrate how feedback from defect inspection equipment can be used to screen incoming substrate wafers and to monitor and optimize the performance of CVD reactors during the epitaxy process.

Major cost gaps were identified from a benchmark (BM) study for a Semiconductor fab. The study triggered deep-dive assessments of both maintenance practices and supply chain business processes. Those assessments uncovered significant improvement opportunities. In this paper, we discuss the approach used to identify and quantify those opportunities, and share important results and observations with the Compound Semiconductor (CS) manufacturing community.

Plasma dicing of silicon wafers is beginning to move from pilot scale into mainstream production. Attention is now focusing on other market sectors which may benefit from a similar dicing approach.  The fragility of GaAs wafers leads to issues (such as wafer breakages, damage to die edges) during conventional wafer saw dicing. Although LASER techniques have been developed, they also have their own drawbacks – specifically sidewall quality.  A systematic investigation of the current capabilities of plasma dicing of GaAs substrates has been performed, developing technology which is both practical and economically viable. Preliminary results show smooth vertical sidewalls of trenches suitable for dicing thinned GaAs substrates at etch rates up to 23μm min^-1.

Traditional in-situ reflectometry sensing at blue (405 nm), red (630 nm) and NIR (950 nm) wavelengths cannot resolve variations in InAlGaN surface roughness or layer thickness with the precision necessary for effective in situ process control. LayTec has developed in situ reflectance metrology at 280 nm to address this need.

We report successful application of in situ UV reflect-ometry and curvature, distinguishing between various phases of strain relaxation and surface relaxation during non-pseudomorphic growth of Al_0.5Ga_0.5N on AlN/sapphire. Results were validated by XRD, TEM and AFM. Results illuminate the influence of reduced TDD on relaxation effects during growth of UVA and UVB LED structures.

GaN power ICs on engineered substrates of Qromis substrate technology (QST^®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm² leakage current at 150 °C. The fabricated 36 mm power HEMTs with L_GD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

A die sort (DS) yield loss forming a ‘starburst’ pattern in a wafermap was observed in a pHEMT technology manufactured by Qorvo. Typical data analysis performed by yield engineers was unable to correlate the failure root cause to a specific process step. To help drive to root cause, Bistel was consulted on the use of eDataLyzer (eDL) software.

This paper will describe the ‘starburst’ DS yield loss pattern in details, followed by the application of Bistel’s eDL software combined with process tool Fault Detection and Correlation (FDC), and end with the validation of the failure mode.

The use of highly-doped thick cap layers is a common strategy to enhance the performance of GaInAs/AlInAs/InP High Electron Mobility Transistors (HEMTs) by reducing the Ohmic contact resistance (R_C). However, because of the high doping level, cap layers become very sensitive to processing steps performed before and during gate recess etching. In this paper, the sensitivity of gate recess etching on a 20 nm highly-doped GaInAs cap layer (doped 7.3 × 10¹⁹ cm^-3) is studied with respect to Ohmic contact type (annealed/non-annealed), chip size, gate finger length, and etchant choice. The use of very high cap doping levels exacerbates device and process scaling challenges. For example, the recess finger length dependence complicates multi-project wafer runs which would simultaneously include narrow finger HEMTs used in digital ICs and longer finger HEMTs used in microwave analog circuits.

The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

The main objective of the Covered Gallium Nitride (CoGaN) project is the demonstration of the electrical performance of a GaN HPA in a frequency range between 25 GHz and 40 GHz with a maximal output power of 5 W in a chip scale packaging technology for 5G applications. In addition, requirements are existing for reliability testing at THB condition of 85°C/85% rel. humidity. In this work a test vehicle circuit with a pre matched 1 mm transistor is used for showing the process feasibility.

In this paper, we report our work on epitaxial growth of InAlN HEMTs for RF device applications.  InAlN HEMTs were grown on 8” high resistivity silicon substrates. Various characterization techniques were used to analyze the quality of the epi wafers. An average sheet resistance (R_sh) of 206Ω/□, with a uniformity of 1.5% (1s/average), indicated a high quality and uniform 2DEG. Hall measurement showed a high sheet charge density of 2.27×10¹³cm⁻² and a mobility of 1430cm²/(Vs). A pit free epi surface was obtained with optimized growth process of the active layers. T-gate RF devices fabricated on the InAlN epi wafers demonstrated an f_T of 250GHz and an f_MAX of 204 GHz, which are the record high values for GaN-based HEMTs on silicon.

In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl₂/BCl₃. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl₂/BCl₃. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

A low- Magnesium (Mg) out-diffusion normally off p-GaN gated AlGaN/GaN high-electron-mobility transistor (HEMT) was developed using a low-temperature laser activation technique. Conventionally, during the actual p-GaN layer activation procedure, Mg out-diffuses into the AlGaN barrier and GaN channel at high temperatures. In addition, the Al of the AlGaN barrier layer is injected into GaN to generate alloy scattering and to suppress current density. In this study, the GaN doped Mg layer (Mg:GaN)was activated using short-wavelength Nd:YAG pulse laser annealing, and a conventional thermal activation device was processed for comparison. The results demonstrated that the laser activation technique in p-GaN HEMT suppressed the Mg out-diffusion-induced leakage current and trapping effect and enhanced the current density and breakdown voltage. Therefore, using this novel technique, a high and active Mg concentration and a favorable doping confinement can be obtained in the p-GaN layer to realize a stable enhancement-mode operation.

GaN power ICs on engineered substrates of Qromis substrate technology (QST^®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm² leakage current at 150 °C. The fabricated 36 mm power HEMTs with L_GD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

In this work we present a systematic study on the conduction properties in vertical GaN trench MISFETs grown and manufactured on different free standing GaN substrates. It is shown that devices manufactured on ammonothermal substrates have superior conduction current density higher than 4 kA/cm², specific on‑state resistance as low as 1.1 ± 0.1 mWcm² and channel sheet resistance of 19.6 ± 0.9 Wmm. It is further shown that scaling these devices to large gate periphery is not limited by current spreading in the drift region, low channel mobility or by self‑heating. The conduction properties of devices manufactured on ammonothermal GaN substrates are found to be the most suitable for pulsed laser driving applications.

GaN is a promising material for more efficient high frequency and high voltage power switching. However, GaN still is not the common material for power electronics due to immature substrate, homoepitaxial growth, and processing technology. Electroluminescence is a promising method to predict failure points due to high field stress, which can assist in the separation of inherent defects stemming from substrate quality, and from process-induced defects as well as identify problems related to proper edge termination design. In this work, we compare the Electroluminescence signatures of devices on inhomogeneous substrates to DC I-V behavior to demonstrate the utility of the technique for process monitoring.

It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

GaN is a promising material for more efficient high frequency and high voltage power switching. However, GaN still is not the common material for power electronics due to immature substrate, homoepitaxial growth, and processing technology. Electroluminescence is a promising method to predict failure points due to high field stress, which can assist in the separation of inherent defects stemming from substrate quality, and from process-induced defects as well as identify problems related to proper edge termination design. In this work, we compare the Electroluminescence signatures of devices on inhomogeneous substrates to DC I-V behavior to demonstrate the utility of the technique for process monitoring.

The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

In this work we present a systematic study on the conduction properties in vertical GaN trench MISFETs grown and manufactured on different free standing GaN substrates. It is shown that devices manufactured on ammonothermal substrates have superior conduction current density higher than 4 kA/cm², specific on‑state resistance as low as 1.1 ± 0.1 mWcm² and channel sheet resistance of 19.6 ± 0.9 Wmm. It is further shown that scaling these devices to large gate periphery is not limited by current spreading in the drift region, low channel mobility or by self‑heating. The conduction properties of devices manufactured on ammonothermal GaN substrates are found to be the most suitable for pulsed laser driving applications.

It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

Plasma dicing of silicon wafers is beginning to move from pilot scale into mainstream production. Attention is now focusing on other market sectors which may benefit from a similar dicing approach.  The fragility of GaAs wafers leads to issues (such as wafer breakages, damage to die edges) during conventional wafer saw dicing. Although LASER techniques have been developed, they also have their own drawbacks – specifically sidewall quality.  A systematic investigation of the current capabilities of plasma dicing of GaAs substrates has been performed, developing technology which is both practical and economically viable. Preliminary results show smooth vertical sidewalls of trenches suitable for dicing thinned GaAs substrates at etch rates up to 23μm min^-1.

The etching of uniform, repeatable GaAs/AlGaAs mesas is an important step in manufacturing VCSELs. This paper presents a high uniformity, low foot etching of mesa structures on 6” wafers. The improved uniformity permits the use of production-friendly optical endpoint techniques which can be used to stop on a specific layer in the VCSEL structure.

Photoelectrochemical (PEC) etching is a promising technology for fabricating GaN devices with low damage. In the simple contactless PEC (CL–PEC) etching process that includes K₂S₂O₈ in the electrolyte as an oxidizing agent, a sample is dipped into the electrolyte under UV irradiation. In this study, we applied CL–PEC to the gate-recess process of GaN HEMTs on an SiC substrate. The etching depth of the recess showed considerable reproducibility by the self-termination feature, and the residual AlGaN layer thickness was approximately 5 nm. The Schottky gate HEMTs with a recessed structure showed the normally off characteristics, and the V_th value was +0.4 V with a standard deviation of ±3.8 mV.

Wet chemical lift off in N-Methyl-2-pyrrolidone (NMP) is widely used in GaN HEMT Front End manufacturing.  In case of a Ti-Al-Ni-Au based metal stack for ohmic contacts, the quality of the lift-off process is much depending on the water content in the solvent NMP. In this paper, it will be shown that the metal stack can be attacked during lift off in NMP with too high water content. Additionally, environmental impacts on the hygroscopy of NMP are investigated in order to keep moisture below a certain level and avoid optical defects on ohmic contacts after lift off.

The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

NGMS reports the maturation of a novel GaN based 3D transistor with state of the art RF switch performance, named the SLCFET (Super Lattice Castellated Field Effect Transistor), with an RF switch FOM greater than 1.8 THz. The configured process has undergone reliability qualification for production.

This report describes the first demonstration of a 100nm T-gate for the Superlattice Castellation Field Effect Transistor (SLCFET) amplifier. The SLCFET amplifier device utilizes a superlattice of GaN/AlGaN channels, which enables a high charge density and low source resistance. A three-dimensional T-gate structure provides electrostatic control of the channels while maintaining high gain. Improvements to the T-gate process have allowed for the scaling of the gate down to 100nm while maintaining excellent gate control, with an on to off current ratio exceeding 10⁷. This gate scaling allows the device to reach F_T / F_MAX of 70/110 GHz with full passivation to maintain compatibility with the productionized SLCFET switch process.

The transistor-injected quantum cascade laser (TI-QCL) is a novel design for a mid-wave infrared (MWIR) laser that seeks to overcome some of the primary limitations of standard quantum cascade lasers (QCLs). By growing the active cascade region within the base-collector junction of an n-p-n heterojunction bipolar transistor (HBT), independent control of the injection current and active region bias is achievable through the emitter current and base-collector reverse bias respectively. The active region bias is important to properly align the lasing states and to control the lasing wavelength. Physical design limitations of the TI-QCL and their effects on the fabrication process of samples is presented. In order to characterize device performance and validate fabrication improvements, InP-based device samples designed for λ = 7.3 µm emission are fabricated. Preliminary characterization results are shown in the form of diode measurements to validate the HBT electrical operation of the TI-QCL which is necessary to realize the optical benefits of the device.

A foundry-ready service in 6-inch InP HBT technology has been developed for mass production in this work. Good uniformity of device performance over 6-inch wafer is obtained. Delicate EPI design with trade-off between cut-off frequency (Ft) and breakdown voltage (BVceo) are devoted to satisfy varieties of demands. We achieved Ft of 175GHz with BVceo of 6.6V and Ft of 100GHz with BVceo of 16V to fulfill the requirements in optical communication and RF power amplifier applications. An advanced sub-micron process is introduced to enhance RF performance for further demands in higher frequency region.

In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al_0.08GaN) of the B.B. more strongly affected the device’ I_on/I_off ratio. It exhibited a low leakage current and high I_on/I_off ratio of approximately 10⁶. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic R_ON. The current gain cut-off frequency (f_T) and maximum stable gain cut-off frequency (f_max) were 5.2 GHz and 10.5 GHz, respectively, for the Al_0.08GaN B.B. device.

Determination of reliability performance over time requires an accurate understanding of device junction temperature, not only in customer use condition, but also during production test and burn-in. Through carefully designed and executed LIV (L=Light, I=current, V=Voltage) measurements and a modeling framework where optical power, thermal and electrical device parameters are interrelated, the laser diode junction temperature, as confirmed by wavelength shift measurements, is obtained via regression of a non-linear self-consistent equation.  Modeled parameters include both threshold current and slope efficiency junction linear temperature dependence coefficients/constants, as well as a thermal impedance factor.

We present a novel heterogeneous photonic integration of III/V on silicon by using epitaxial regrowth on III/V-on-Si wafer bonded substrates. This integration method decouples the correlated root causes, i.e., lattice, thermal, and domain mismatches, which are all responsible for a large number of detrimental dislocations in the heteroepitaxial process.  The grown multi-quantum well vertical p–i–n diode laser structure shows a significantly low dislocation density of 9.5 × 10⁴ cm⁻², two orders of magnitude lower than the state-of-the-art conventional monolithic growth of III/V on Si. Hybrid InP-on-Si multi-quantum well lasers were successfully demonstrated with this heterogeneous integration and shown room-temperature pulsed and continuous-wave lasing. This generic concept can be applied to other material systems to provide higher integration density, more functionalities and lower total cost for photonics as well as microelectronics, MEMS, and many other applications.

In this study, a 50-nm Al_0.05Ga_0.95N back barrier (BB) layer was used in an AlGaN/GaN high-electron-mobility transistor between the two-dimensional electron gas channel and Fe-doped/C-doped buffer layers. This BB layer can reduce the channel layer. The BB layer is affected by doped carriers in the buffer layer and the conduction energy band between the channel and the buffer layers. The I_on/I_off ratio of the BB device was 3.43 × 10⁵ and the ratio for the device without BB was 1.91 × 10³. Lower leakage currents were obtained in the BB device because of the higher conduction energy band. The 0.25-μm gate length device with the BB exhibited a high current gain cutoff frequency of 26.9 GHz and power gain cutoff frequency of 54.7 GHz.

In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al_0.08GaN) of the B.B. more strongly affected the device’ I_on/I_off ratio. It exhibited a low leakage current and high I_on/I_off ratio of approximately 10⁶. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic R_ON. The current gain cut-off frequency (f_T) and maximum stable gain cut-off frequency (f_max) were 5.2 GHz and 10.5 GHz, respectively, for the Al_0.08GaN B.B. device.

In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al_0.08GaN) of the B.B. more strongly affected the device’ I_on/I_off ratio. It exhibited a low leakage current and high I_on/I_off ratio of approximately 10⁶. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic R_ON. The current gain cut-off frequency (f_T) and maximum stable gain cut-off frequency (f_max) were 5.2 GHz and 10.5 GHz, respectively, for the Al_0.08GaN B.B. device.

Wet chemical lift off in N-Methyl-2-pyrrolidone (NMP) is widely used in GaN HEMT Front End manufacturing.  In case of a Ti-Al-Ni-Au based metal stack for ohmic contacts, the quality of the lift-off process is much depending on the water content in the solvent NMP. In this paper, it will be shown that the metal stack can be attacked during lift off in NMP with too high water content. Additionally, environmental impacts on the hygroscopy of NMP are investigated in order to keep moisture below a certain level and avoid optical defects on ohmic contacts after lift off.

The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

Photoelectrochemical (PEC) etching is a promising technology for fabricating GaN devices with low damage. In the simple contactless PEC (CL–PEC) etching process that includes K₂S₂O₈ in the electrolyte as an oxidizing agent, a sample is dipped into the electrolyte under UV irradiation. In this study, we applied CL–PEC to the gate-recess process of GaN HEMTs on an SiC substrate. The etching depth of the recess showed considerable reproducibility by the self-termination feature, and the residual AlGaN layer thickness was approximately 5 nm. The Schottky gate HEMTs with a recessed structure showed the normally off characteristics, and the V_th value was +0.4 V with a standard deviation of ±3.8 mV.

This work describes an on-going effort to develop and mature a 140 nm GaN MMIC technology with a focus on efficient power amplification at frequencies ranging from DC to 50 GHz and a 90 nm technology targeted towards V- and W-band applications, and then release the technologies within a foundry process that is open to the DoD community.

Photoelectrochemical (PEC) etching is a promising technology for fabricating GaN devices with low damage. In the simple contactless PEC (CL–PEC) etching process that includes K₂S₂O₈ in the electrolyte as an oxidizing agent, a sample is dipped into the electrolyte under UV irradiation. In this study, we applied CL–PEC to the gate-recess process of GaN HEMTs on an SiC substrate. The etching depth of the recess showed considerable reproducibility by the self-termination feature, and the residual AlGaN layer thickness was approximately 5 nm. The Schottky gate HEMTs with a recessed structure showed the normally off characteristics, and the V_th value was +0.4 V with a standard deviation of ±3.8 mV.

In order to meet the forecast growing demand of n⁺ SiC material, wafer suppliers will need to implement new metrology techniques to allow the detection of crystalline defects and ensure the quality of their materials. Incumbent techniques such as KOH etching have been used for many years but remain very costly as the wafers cannot be processed further. Alternative techniques such as X-ray Diffraction Imaging (X-ray Topography) can be used to detect crystalline defects non-destructively but studies have been limited to synchrotron radiation which cannot be used as an in-line characterization. In this paper, Bruker have used novel equipment (Sensus-CS) to study the correlation between laboratory X-ray Diffraction Imaging and KOH etching performed at the University of Warwick.

In this work we present a systematic study on the conduction properties in vertical GaN trench MISFETs grown and manufactured on different free standing GaN substrates. It is shown that devices manufactured on ammonothermal substrates have superior conduction current density higher than 4 kA/cm², specific on‑state resistance as low as 1.1 ± 0.1 mWcm² and channel sheet resistance of 19.6 ± 0.9 Wmm. It is further shown that scaling these devices to large gate periphery is not limited by current spreading in the drift region, low channel mobility or by self‑heating. The conduction properties of devices manufactured on ammonothermal GaN substrates are found to be the most suitable for pulsed laser driving applications.

In this paper, we report our work on epitaxial growth of InAlN HEMTs for RF device applications.  InAlN HEMTs were grown on 8” high resistivity silicon substrates. Various characterization techniques were used to analyze the quality of the epi wafers. An average sheet resistance (R_sh) of 206Ω/□, with a uniformity of 1.5% (1s/average), indicated a high quality and uniform 2DEG. Hall measurement showed a high sheet charge density of 2.27×10¹³cm⁻² and a mobility of 1430cm²/(Vs). A pit free epi surface was obtained with optimized growth process of the active layers. T-gate RF devices fabricated on the InAlN epi wafers demonstrated an f_T of 250GHz and an f_MAX of 204 GHz, which are the record high values for GaN-based HEMTs on silicon.

The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

A die sort (DS) yield loss forming a ‘starburst’ pattern in a wafermap was observed in a pHEMT technology manufactured by Qorvo. Typical data analysis performed by yield engineers was unable to correlate the failure root cause to a specific process step. To help drive to root cause, Bistel was consulted on the use of eDataLyzer (eDL) software.

This paper will describe the ‘starburst’ DS yield loss pattern in details, followed by the application of Bistel’s eDL software combined with process tool Fault Detection and Correlation (FDC), and end with the validation of the failure mode.

The RF harmonic distortion of coplanar waveguides (CPWs) fabricated on AlGaN/GaN HEMT heterostructures grown on both high-resistivity Si (GaN-on-Si) and semi-insulating SiC (GaN-on-SiC) substrates is reported for the first time. The loss performance and the nonlinear behavior of the CPW lines were experimentally characterized using both small- and large-signal measurements. From 100 MHz to 20 GHz, low loss (less than 0.3 dB/mm at 20 GHz) was achieved; the attenuation of CPW lines on the GaN-on-Si substrate is ~0.05 dB/mm higher than that of the GaN-on-SiC substrate. The harmonic distortion levels of the GaN-on-Si substrate and GaN-on-SiC were also evaluated experimentally; in contrast to the small-signal loss, more significant differences in second- and third-order nonlinearity, and thus intermodulation, are observed between Si and SiC substrates. Large-signal characterization of the GaN-on-Si substrate was carried out over temperature from 25 °C to 175 °C.  Due to increases in substrate conductivity with temperature, the harmonic distortion levels are found to increase significantly at temperatures above 75 °C.

The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

This work focuses on evaluating and demonstrating channeled p-type and n-type implantations in silicon carbide in a repeatable mass-production environment. Range increase of about 3X is observed using channeled conditions as opposed to normal incident conditions for both Aluminum and Phosphorous. The various advantages enabled by this technology for advanced device designs are highlighted. Super-junction devices targeting the same voltage range can be fabricated using 1 or 2 lesser epitaxial regrowth layers.

SiN films were grown in a production scale vertical MOCVD reactor and studied for in-situ passivation of III-nitride HEMT structures. The SiN was near-stoichiometric in composition and uniform in thickness across 4-, 6- and 8-inch diameter substrates. Its surface exhibited low roughness of about 0.3nm when the films were grown using H₂ carrier gas. Contamination of the SiN with Al and Ga elements was as low as 1e16cm^-3 and the H concentration was approximately 1at.% when optimized growth conditions were employed. It was demonstrated that the density of states at the SiN/III-nitride interface can be controlled by SiN growth conditions.

Homoepitaxial GaN growth was implemented, studied, and improved in a production scale MOCVD reactor. The epitaxial GaN threading dislocation density was very close to that of the different free-standing GaN substrates and uniform across large diameters. We were able to limit incorporation of impurities to the low levels required for vertical electron drift layers by using appropriate growth process conditions. Different surface analysis studies revealed near-perfect step flow growth over large areas of the wafers.

SiN films were grown in a production scale vertical MOCVD reactor and studied for in-situ passivation of III-nitride HEMT structures. The SiN was near-stoichiometric in composition and uniform in thickness across 4-, 6- and 8-inch diameter substrates. Its surface exhibited low roughness of about 0.3nm when the films were grown using H₂ carrier gas. Contamination of the SiN with Al and Ga elements was as low as 1e16cm^-3 and the H concentration was approximately 1at.% when optimized growth conditions were employed. It was demonstrated that the density of states at the SiN/III-nitride interface can be controlled by SiN growth conditions.

Homoepitaxial GaN growth was implemented, studied, and improved in a production scale MOCVD reactor. The epitaxial GaN threading dislocation density was very close to that of the different free-standing GaN substrates and uniform across large diameters. We were able to limit incorporation of impurities to the low levels required for vertical electron drift layers by using appropriate growth process conditions. Different surface analysis studies revealed near-perfect step flow growth over large areas of the wafers.

Major cost gaps were identified from a benchmark (BM) study for a Semiconductor fab. The study triggered deep-dive assessments of both maintenance practices and supply chain business processes. Those assessments uncovered significant improvement opportunities. In this paper, we discuss the approach used to identify and quantify those opportunities, and share important results and observations with the Compound Semiconductor (CS) manufacturing community.

NiCr is one of the most commonly used resistive materials for fabricating precision thin film resistors due to its wide range of resistivity, low temperature coefficient of resistivity (TCR), and high stability of electrical properties. NiCr thin film resistors are usually manufactured by evaporation or sputtering. It is well known that thermal evaporation of NiCr from a finite mass of molten alloy causes a film composition change away from the composition of the source, as well as film composition changes from run to run. Some electrical properties of NiCr thin film resistors strongly depend on the film microstructure (i.e. Ni:Cr ratio) in addition to its spatial geometry (film thickness) and the deposition parameters in the evaporator. As a result, while film thickness and deposition parameters are well controlled, often time resistivity of evaporated NiCr thin film resistors goes out of spec. Therefore, in this paper we are investigating the possibility of replacing the evaporated NiCr thin films with the sputtered NiCr thin films as resistors. Here, we present a comprehensive study of NiCr thin film resistors developed using DC sputtering system and discuss the effects of sputtering process parameters and substrate conditions on film microstructure, TCR and electrical properties.

The transistor-injected quantum cascade laser (TI-QCL) is a novel design for a mid-wave infrared (MWIR) laser that seeks to overcome some of the primary limitations of standard quantum cascade lasers (QCLs). By growing the active cascade region within the base-collector junction of an n-p-n heterojunction bipolar transistor (HBT), independent control of the injection current and active region bias is achievable through the emitter current and base-collector reverse bias respectively. The active region bias is important to properly align the lasing states and to control the lasing wavelength. Physical design limitations of the TI-QCL and their effects on the fabrication process of samples is presented. In order to characterize device performance and validate fabrication improvements, InP-based device samples designed for λ = 7.3 µm emission are fabricated. Preliminary characterization results are shown in the form of diode measurements to validate the HBT electrical operation of the TI-QCL which is necessary to realize the optical benefits of the device.

Transphorm is supplying N-polar GaN on SiC and sapphire epitaxial wafers for customers developing ultra-high performance RF and mm-wave electronics devices. The manufacturing process is SPC controlled and DOE optimized, and the wafers exhibit very high 2DEG electron mobility and excellent thickness and R_sh uniformities.

The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

Pad conditioning is critical to maintaining the required process stability and performance in semiconductor CMP. As the process and performance requirements for substrate polishing in the compound semiconductor industry become more stringent, we believe there are significant opportunities for improvement via more extensive adoption of optimized pad conditioning protocols. In this paper we will review the pertinent state of the art in semiconductor CMP and propose some specific target areas for adoption in compound semiconductor substrate polishing.

It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

Bulk induced dynamic R_ON in GaN-on-Si HEMTs is a serious performance limiting instability which remains a problem even in some commercially available power switching devices. Its origin is now reasonably well understood, however until now it has not been possible to simulate it using a realistic epitaxial stack. For the first time we successfully simulate the controlled suppression of bulk dynamic R_ON by adding a specific model for leakage along threading dislocations. This was undertaken using a commercially available standard TCAD simulator, allowing realistic device optimization in an advanced GaN HEMT design flow.

A nanoindentation induced blistering method has been used to extract the GaN/diamond interfacial toughness (adhesion energy) from four types of GaN-on-diamond samples with varying SiN_x interlayer thicknesses. The mode I energy release rate (G_IC) was quantified and is presented. Additionally, transient thermoreflectance has been used to measure the thermal boundary resistance (TBR) between the GaN and the diamond substrate. It was found that a thin SiN_x interlayer resulted in a lower TBR (15 m² K GW^-1) whilst maintaining a reasonable interfacial toughness (1.4±0.5 J m^-2). For interlayers of a similar thickness, samples with a high interfacial toughness and high residual stresses in the GaN had a smaller TBR. This indicates that the intrinsic interfacial characteristics that enhanced the interfacial toughness could be beneficial in improving the TBR.

In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl₂/BCl₃. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl₂/BCl₃. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

We present a novel heterogeneous photonic integration of III/V on silicon by using epitaxial regrowth on III/V-on-Si wafer bonded substrates. This integration method decouples the correlated root causes, i.e., lattice, thermal, and domain mismatches, which are all responsible for a large number of detrimental dislocations in the heteroepitaxial process.  The grown multi-quantum well vertical p–i–n diode laser structure shows a significantly low dislocation density of 9.5 × 10⁴ cm⁻², two orders of magnitude lower than the state-of-the-art conventional monolithic growth of III/V on Si. Hybrid InP-on-Si multi-quantum well lasers were successfully demonstrated with this heterogeneous integration and shown room-temperature pulsed and continuous-wave lasing. This generic concept can be applied to other material systems to provide higher integration density, more functionalities and lower total cost for photonics as well as microelectronics, MEMS, and many other applications.

The issues of achieving good isolation and low leakage for complex integrated circuits such as stacked HBT on HEMT (BiHEMT) epitaxial GaAs semiconductor devices are described in this paper. The need for achieving a balance between short cycle time and optimum performance by use of appropriate ion implant species and schedules (energy/dose) are discussed in detail.

This work focuses on evaluating and demonstrating channeled p-type and n-type implantations in silicon carbide in a repeatable mass-production environment. Range increase of about 3X is observed using channeled conditions as opposed to normal incident conditions for both Aluminum and Phosphorous. The various advantages enabled by this technology for advanced device designs are highlighted. Super-junction devices targeting the same voltage range can be fabricated using 1 or 2 lesser epitaxial regrowth layers.

The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

SiN films were grown in a production scale vertical MOCVD reactor and studied for in-situ passivation of III-nitride HEMT structures. The SiN was near-stoichiometric in composition and uniform in thickness across 4-, 6- and 8-inch diameter substrates. Its surface exhibited low roughness of about 0.3nm when the films were grown using H₂ carrier gas. Contamination of the SiN with Al and Ga elements was as low as 1e16cm^-3 and the H concentration was approximately 1at.% when optimized growth conditions were employed. It was demonstrated that the density of states at the SiN/III-nitride interface can be controlled by SiN growth conditions.

Homoepitaxial GaN growth was implemented, studied, and improved in a production scale MOCVD reactor. The epitaxial GaN threading dislocation density was very close to that of the different free-standing GaN substrates and uniform across large diameters. We were able to limit incorporation of impurities to the low levels required for vertical electron drift layers by using appropriate growth process conditions. Different surface analysis studies revealed near-perfect step flow growth over large areas of the wafers.

In order to meet the forecast growing demand of n⁺ SiC material, wafer suppliers will need to implement new metrology techniques to allow the detection of crystalline defects and ensure the quality of their materials. Incumbent techniques such as KOH etching have been used for many years but remain very costly as the wafers cannot be processed further. Alternative techniques such as X-ray Diffraction Imaging (X-ray Topography) can be used to detect crystalline defects non-destructively but studies have been limited to synchrotron radiation which cannot be used as an in-line characterization. In this paper, Bruker have used novel equipment (Sensus-CS) to study the correlation between laboratory X-ray Diffraction Imaging and KOH etching performed at the University of Warwick.

In this work we compare non-contact charge-voltage imaging and UV-photoluminescence (UV-PL) imaging of yield killer defects in epitaxial 4H-SiC wafers.  Two significant findings are based on macro- and micro-scale imaging, respectively.  1- Whole wafer images demonstrate that only a fraction of the UV-PL defects in triangular, downfall and carrot categories are electrically active. 2- Micro-scale images reveal similarities and differences between PL and electrical defect images.  Presented for the first time, micrometer resolution leakage patterns within triangular defects are consistent with the microstructure modeling in reference 1. The results imply that the depletion layer leakage within killer defects corresponds to exposed 3C-SiC polytypes. This leakage may be a consequence of the lower 2.2eV energy gap of 3C-SiC compared to 3.3eV in 4H-SiC.

Pad conditioning is critical to maintaining the required process stability and performance in semiconductor CMP. As the process and performance requirements for substrate polishing in the compound semiconductor industry become more stringent, we believe there are significant opportunities for improvement via more extensive adoption of optimized pad conditioning protocols. In this paper we will review the pertinent state of the art in semiconductor CMP and propose some specific target areas for adoption in compound semiconductor substrate polishing.

We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

In this work, we present an overview of WIN’s latest generation of 0.15-mm GaAs pHEMT technology specifically optimized for highly linear PAs for advanced mm-wave communication systems. When compared with the prior technology PP15-51 at either 5.8 or 29 GHz, the new technology PP15-61 outperforms the prior one in multiple respects, including enhanced P_out, an additional linear gain of > 1 dB, a 10 percentage point increase in peak PAE (from ≈ 44% to ≈ 54% at 29 GHz), and, most notably, an improvement of ≈ 3 dB in OIP3 when operated in the linear regions at 29 GHz. As part of routine characterization, the IMD3 asymmetry was further compared for both technologies. Its behavior can be descriptively interpreted in terms of a physical scenario considering effects due to charge trapping, thermal properties, and the bias networks used in the measurements.

The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

As we step into the era of Smart Manufacturing, a growing number of manufacturers across all industries are leveraging enabling technologies, such as Artificial intelligence (AI), Cloud, and Internet of Things (IOT), to help them improve productivity and profitability. Through an actual use case, this paper illustrates how one of these enabling technologies, Cloud computing, helps a semiconductor manufacturer overcome various challenges allowing them to be more productive and cost efficient.

The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

In this paper, we report our work on epitaxial growth of InAlN HEMTs for RF device applications.  InAlN HEMTs were grown on 8” high resistivity silicon substrates. Various characterization techniques were used to analyze the quality of the epi wafers. An average sheet resistance (R_sh) of 206Ω/□, with a uniformity of 1.5% (1s/average), indicated a high quality and uniform 2DEG. Hall measurement showed a high sheet charge density of 2.27×10¹³cm⁻² and a mobility of 1430cm²/(Vs). A pit free epi surface was obtained with optimized growth process of the active layers. T-gate RF devices fabricated on the InAlN epi wafers demonstrated an f_T of 250GHz and an f_MAX of 204 GHz, which are the record high values for GaN-based HEMTs on silicon.

The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

This work characterizes the effects of gate-length (L_G) scaling in a self-aligned gate (SAG) β-Ga₂O₃ MOSFET process. Additional performance gains are expected by extending the SAG process from large L_G to sub-micrometer dimensions.  This data incorporates L_G scaling down to 200 nm to improve device performance in Ga₂O₃ SAG MOSFETs using a stepper lithography process to define sub-micron gate lengths.

NGMS reports the maturation of a novel GaN based 3D transistor with state of the art RF switch performance, named the SLCFET (Super Lattice Castellated Field Effect Transistor), with an RF switch FOM greater than 1.8 THz. The configured process has undergone reliability qualification for production.

In this paper, we report our work on epitaxial growth of InAlN HEMTs for RF device applications.  InAlN HEMTs were grown on 8” high resistivity silicon substrates. Various characterization techniques were used to analyze the quality of the epi wafers. An average sheet resistance (R_sh) of 206Ω/□, with a uniformity of 1.5% (1s/average), indicated a high quality and uniform 2DEG. Hall measurement showed a high sheet charge density of 2.27×10¹³cm⁻² and a mobility of 1430cm²/(Vs). A pit free epi surface was obtained with optimized growth process of the active layers. T-gate RF devices fabricated on the InAlN epi wafers demonstrated an f_T of 250GHz and an f_MAX of 204 GHz, which are the record high values for GaN-based HEMTs on silicon.

In this work, we present an overview of WIN’s latest generation of 0.15-mm GaAs pHEMT technology specifically optimized for highly linear PAs for advanced mm-wave communication systems. When compared with the prior technology PP15-51 at either 5.8 or 29 GHz, the new technology PP15-61 outperforms the prior one in multiple respects, including enhanced P_out, an additional linear gain of > 1 dB, a 10 percentage point increase in peak PAE (from ≈ 44% to ≈ 54% at 29 GHz), and, most notably, an improvement of ≈ 3 dB in OIP3 when operated in the linear regions at 29 GHz. As part of routine characterization, the IMD3 asymmetry was further compared for both technologies. Its behavior can be descriptively interpreted in terms of a physical scenario considering effects due to charge trapping, thermal properties, and the bias networks used in the measurements.

GaN power ICs on engineered substrates of Qromis substrate technology (QST^®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm² leakage current at 150 °C. The fabricated 36 mm power HEMTs with L_GD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

GaN power ICs on engineered substrates of Qromis substrate technology (QST^®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm² leakage current at 150 °C. The fabricated 36 mm power HEMTs with L_GD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

MicroLED is considered as the next generation display technology, since MicroLED display has high brightness, wide color gamut, high aperture ratio, and good reliability.  MicroLED display can be used for both current applications and innovative display technology. Based on our proprietary PixeLED^® display technology and SMAR·Tech^TM repair solution, we have demonstrated high transparency borderless active-matrix MicroLED display.

We present a novel heterogeneous photonic integration of III/V on silicon by using epitaxial regrowth on III/V-on-Si wafer bonded substrates. This integration method decouples the correlated root causes, i.e., lattice, thermal, and domain mismatches, which are all responsible for a large number of detrimental dislocations in the heteroepitaxial process.  The grown multi-quantum well vertical p–i–n diode laser structure shows a significantly low dislocation density of 9.5 × 10⁴ cm⁻², two orders of magnitude lower than the state-of-the-art conventional monolithic growth of III/V on Si. Hybrid InP-on-Si multi-quantum well lasers were successfully demonstrated with this heterogeneous integration and shown room-temperature pulsed and continuous-wave lasing. This generic concept can be applied to other material systems to provide higher integration density, more functionalities and lower total cost for photonics as well as microelectronics, MEMS, and many other applications.

A foundry-ready service in 6-inch InP HBT technology has been developed for mass production in this work. Good uniformity of device performance over 6-inch wafer is obtained. Delicate EPI design with trade-off between cut-off frequency (Ft) and breakdown voltage (BVceo) are devoted to satisfy varieties of demands. We achieved Ft of 175GHz with BVceo of 6.6V and Ft of 100GHz with BVceo of 16V to fulfill the requirements in optical communication and RF power amplifier applications. An advanced sub-micron process is introduced to enhance RF performance for further demands in higher frequency region.

This work characterizes the effects of gate-length (L_G) scaling in a self-aligned gate (SAG) β-Ga₂O₃ MOSFET process. Additional performance gains are expected by extending the SAG process from large L_G to sub-micrometer dimensions.  This data incorporates L_G scaling down to 200 nm to improve device performance in Ga₂O₃ SAG MOSFETs using a stepper lithography process to define sub-micron gate lengths.

To produce high performance AlGaN/GaN heterostructure field effect transistors for RF power applications, one of the critical control parameters of AlGaN/GaN system is the contact resistance (Rc) of the ohmic metal to AlGaN. In the present study, two important factors for the contact resistance, a Ti₃AlN interfacial layer and TiN islands were investigated using phase identification, and morphology as determined by Nano Beam Electron Diffraction (NBD) technique in transmission electron microscopy. Based on our study, both Ti₃AlN interfacial layer and TiN islands contribute to ohmic contact behavior in the system.

To produce high performance AlGaN/GaN heterostructure field effect transistors for RF power applications, one of the critical control parameters of AlGaN/GaN system is the contact resistance (Rc) of the ohmic metal to AlGaN. In the present study, two important factors for the contact resistance, a Ti₃AlN interfacial layer and TiN islands were investigated using phase identification, and morphology as determined by Nano Beam Electron Diffraction (NBD) technique in transmission electron microscopy. Based on our study, both Ti₃AlN interfacial layer and TiN islands contribute to ohmic contact behavior in the system.

A foundry-ready service in 6-inch InP HBT technology has been developed for mass production in this work. Good uniformity of device performance over 6-inch wafer is obtained. Delicate EPI design with trade-off between cut-off frequency (Ft) and breakdown voltage (BVceo) are devoted to satisfy varieties of demands. We achieved Ft of 175GHz with BVceo of 6.6V and Ft of 100GHz with BVceo of 16V to fulfill the requirements in optical communication and RF power amplifier applications. An advanced sub-micron process is introduced to enhance RF performance for further demands in higher frequency region.

A foundry-ready service in 6-inch InP HBT technology has been developed for mass production in this work. Good uniformity of device performance over 6-inch wafer is obtained. Delicate EPI design with trade-off between cut-off frequency (Ft) and breakdown voltage (BVceo) are devoted to satisfy varieties of demands. We achieved Ft of 175GHz with BVceo of 6.6V and Ft of 100GHz with BVceo of 16V to fulfill the requirements in optical communication and RF power amplifier applications. An advanced sub-micron process is introduced to enhance RF performance for further demands in higher frequency region.

The high growth of the EV/HEV market impacted significantly the wide bandgap semiconductor industry, creating new opportunities and a competition between SiC and GaN in many applications such as on-board chargers, DC-DC converters and main inverters. This paper provides an overview of SiC and GaN device technology, including Yole Développement’s understanding of the market’s current dynamics and future evolution of wide band gap materials compared to mainstream Silicon power electronics market.

The paper presents the market overview of different compound semiconductor such as GaN, GaAs, and InP impacted by the deployment of 5G in wireless infrastructure. The value chain from wafer and epitaxy to device level is covered, as well as technology and market trends and Yole’s forecast for the coming years.

In this work, we present an overview of WIN’s latest generation of 0.15-mm GaAs pHEMT technology specifically optimized for highly linear PAs for advanced mm-wave communication systems. When compared with the prior technology PP15-51 at either 5.8 or 29 GHz, the new technology PP15-61 outperforms the prior one in multiple respects, including enhanced P_out, an additional linear gain of > 1 dB, a 10 percentage point increase in peak PAE (from ≈ 44% to ≈ 54% at 29 GHz), and, most notably, an improvement of ≈ 3 dB in OIP3 when operated in the linear regions at 29 GHz. As part of routine characterization, the IMD3 asymmetry was further compared for both technologies. Its behavior can be descriptively interpreted in terms of a physical scenario considering effects due to charge trapping, thermal properties, and the bias networks used in the measurements.

In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al_0.08GaN) of the B.B. more strongly affected the device’ I_on/I_off ratio. It exhibited a low leakage current and high I_on/I_off ratio of approximately 10⁶. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic R_ON. The current gain cut-off frequency (f_T) and maximum stable gain cut-off frequency (f_max) were 5.2 GHz and 10.5 GHz, respectively, for the Al_0.08GaN B.B. device.

In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al_0.08GaN) of the B.B. more strongly affected the device’ I_on/I_off ratio. It exhibited a low leakage current and high I_on/I_off ratio of approximately 10⁶. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic R_ON. The current gain cut-off frequency (f_T) and maximum stable gain cut-off frequency (f_max) were 5.2 GHz and 10.5 GHz, respectively, for the Al_0.08GaN B.B. device.

A low- Magnesium (Mg) out-diffusion normally off p-GaN gated AlGaN/GaN high-electron-mobility transistor (HEMT) was developed using a low-temperature laser activation technique. Conventionally, during the actual p-GaN layer activation procedure, Mg out-diffuses into the AlGaN barrier and GaN channel at high temperatures. In addition, the Al of the AlGaN barrier layer is injected into GaN to generate alloy scattering and to suppress current density. In this study, the GaN doped Mg layer (Mg:GaN)was activated using short-wavelength Nd:YAG pulse laser annealing, and a conventional thermal activation device was processed for comparison. The results demonstrated that the laser activation technique in p-GaN HEMT suppressed the Mg out-diffusion-induced leakage current and trapping effect and enhanced the current density and breakdown voltage. Therefore, using this novel technique, a high and active Mg concentration and a favorable doping confinement can be obtained in the p-GaN layer to realize a stable enhancement-mode operation.

Metal–insulator–semiconductor p-type GaN high-electron-mobility transistor with an Al₂O₃/AlN deposited by atomic layer deposition was investigated. The selected insulator, AlN has been proven to have a good interface with GaN. A traditional p-GaN device without an Al₂O₃/AlN layer was processed for comparison. Due to the Al₂O₃/AlN layer, the gate leakage was lower, and the threshold voltage was higher, at 4.7 V. Additionally, excellent turn-on voltage was obtained. Furthermore, low current degradation and smaller V_TH shift at high temperatures was also observed. Hence, growing a good-quality Al₂O₃/AlN layer can achieve an enhancement-mode operation with superior stability and high gate swing region.

In this study, a 50-nm Al_0.05Ga_0.95N back barrier (BB) layer was used in an AlGaN/GaN high-electron-mobility transistor between the two-dimensional electron gas channel and Fe-doped/C-doped buffer layers. This BB layer can reduce the channel layer. The BB layer is affected by doped carriers in the buffer layer and the conduction energy band between the channel and the buffer layers. The I_on/I_off ratio of the BB device was 3.43 × 10⁵ and the ratio for the device without BB was 1.91 × 10³. Lower leakage currents were obtained in the BB device because of the higher conduction energy band. The 0.25-μm gate length device with the BB exhibited a high current gain cutoff frequency of 26.9 GHz and power gain cutoff frequency of 54.7 GHz.

A nanoindentation induced blistering method has been used to extract the GaN/diamond interfacial toughness (adhesion energy) from four types of GaN-on-diamond samples with varying SiN_x interlayer thicknesses. The mode I energy release rate (G_IC) was quantified and is presented. Additionally, transient thermoreflectance has been used to measure the thermal boundary resistance (TBR) between the GaN and the diamond substrate. It was found that a thin SiN_x interlayer resulted in a lower TBR (15 m² K GW^-1) whilst maintaining a reasonable interfacial toughness (1.4±0.5 J m^-2). For interlayers of a similar thickness, samples with a high interfacial toughness and high residual stresses in the GaN had a smaller TBR. This indicates that the intrinsic interfacial characteristics that enhanced the interfacial toughness could be beneficial in improving the TBR.

In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al_0.08GaN) of the B.B. more strongly affected the device’ I_on/I_off ratio. It exhibited a low leakage current and high I_on/I_off ratio of approximately 10⁶. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic R_ON. The current gain cut-off frequency (f_T) and maximum stable gain cut-off frequency (f_max) were 5.2 GHz and 10.5 GHz, respectively, for the Al_0.08GaN B.B. device.

In this work, we present an overview of WIN’s latest generation of 0.15-mm GaAs pHEMT technology specifically optimized for highly linear PAs for advanced mm-wave communication systems. When compared with the prior technology PP15-51 at either 5.8 or 29 GHz, the new technology PP15-61 outperforms the prior one in multiple respects, including enhanced P_out, an additional linear gain of > 1 dB, a 10 percentage point increase in peak PAE (from ≈ 44% to ≈ 54% at 29 GHz), and, most notably, an improvement of ≈ 3 dB in OIP3 when operated in the linear regions at 29 GHz. As part of routine characterization, the IMD3 asymmetry was further compared for both technologies. Its behavior can be descriptively interpreted in terms of a physical scenario considering effects due to charge trapping, thermal properties, and the bias networks used in the measurements.

Transphorm is supplying N-polar GaN on SiC and sapphire epitaxial wafers for customers developing ultra-high performance RF and mm-wave electronics devices. The manufacturing process is SPC controlled and DOE optimized, and the wafers exhibit very high 2DEG electron mobility and excellent thickness and R_sh uniformities.

MicroLED is considered as the next generation display technology, since MicroLED display has high brightness, wide color gamut, high aperture ratio, and good reliability.  MicroLED display can be used for both current applications and innovative display technology. Based on our proprietary PixeLED^® display technology and SMAR·Tech^TM repair solution, we have demonstrated high transparency borderless active-matrix MicroLED display.

This work describes an on-going effort to develop and mature a 140 nm GaN MMIC technology with a focus on efficient power amplification at frequencies ranging from DC to 50 GHz and a 90 nm technology targeted towards V- and W-band applications, and then release the technologies within a foundry process that is open to the DoD community.

In this work fabrication of MISCAP structures was achieved on n-type gallium nitride using atomic layer deposited silicon nitride as the dielectric layer and sputtered ruthenium contacts. Preliminary values extracted from C-f data suggests very high capacitance densities up to 3.18 μF∙cm^-2 and very high accumulation-mode field effect mobility, as high as 325 cm²V^-1s^-1 at a bias voltage of 2.5 V.

GaN power ICs on engineered substrates of Qromis substrate technology (QST^®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm² leakage current at 150 °C. The fabricated 36 mm power HEMTs with L_GD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl₂/BCl₃. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl₂/BCl₃. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

The paper presents the market overview of different compound semiconductor such as GaN, GaAs, and InP impacted by the deployment of 5G in wireless infrastructure. The value chain from wafer and epitaxy to device level is covered, as well as technology and market trends and Yole’s forecast for the coming years.

This work focuses on evaluating and demonstrating channeled p-type and n-type implantations in silicon carbide in a repeatable mass-production environment. Range increase of about 3X is observed using channeled conditions as opposed to normal incident conditions for both Aluminum and Phosphorous. The various advantages enabled by this technology for advanced device designs are highlighted. Super-junction devices targeting the same voltage range can be fabricated using 1 or 2 lesser epitaxial regrowth layers.

The MAX group was hired to provide transitional leadership and to improve fundamental performance of a legacy photonics fab. Over a six-month time-frame, weekly output increased by 32% and cycle time was cut by 46%. This paper will discuss the approach taken to transform the fab.

SiN films were grown in a production scale vertical MOCVD reactor and studied for in-situ passivation of III-nitride HEMT structures. The SiN was near-stoichiometric in composition and uniform in thickness across 4-, 6- and 8-inch diameter substrates. Its surface exhibited low roughness of about 0.3nm when the films were grown using H₂ carrier gas. Contamination of the SiN with Al and Ga elements was as low as 1e16cm^-3 and the H concentration was approximately 1at.% when optimized growth conditions were employed. It was demonstrated that the density of states at the SiN/III-nitride interface can be controlled by SiN growth conditions.

Homoepitaxial GaN growth was implemented, studied, and improved in a production scale MOCVD reactor. The epitaxial GaN threading dislocation density was very close to that of the different free-standing GaN substrates and uniform across large diameters. We were able to limit incorporation of impurities to the low levels required for vertical electron drift layers by using appropriate growth process conditions. Different surface analysis studies revealed near-perfect step flow growth over large areas of the wafers.

The RF harmonic distortion of coplanar waveguides (CPWs) fabricated on AlGaN/GaN HEMT heterostructures grown on both high-resistivity Si (GaN-on-Si) and semi-insulating SiC (GaN-on-SiC) substrates is reported for the first time. The loss performance and the nonlinear behavior of the CPW lines were experimentally characterized using both small- and large-signal measurements. From 100 MHz to 20 GHz, low loss (less than 0.3 dB/mm at 20 GHz) was achieved; the attenuation of CPW lines on the GaN-on-Si substrate is ~0.05 dB/mm higher than that of the GaN-on-SiC substrate. The harmonic distortion levels of the GaN-on-Si substrate and GaN-on-SiC were also evaluated experimentally; in contrast to the small-signal loss, more significant differences in second- and third-order nonlinearity, and thus intermodulation, are observed between Si and SiC substrates. Large-signal characterization of the GaN-on-Si substrate was carried out over temperature from 25 °C to 175 °C.  Due to increases in substrate conductivity with temperature, the harmonic distortion levels are found to increase significantly at temperatures above 75 °C.