• Afroz, Shamima

    Northrop Grumman
    • Formation of Diamond Superjunctions to Enable GaN-Based Super-Lattice Power Amplifiers with Diamond Enhanced Superjunctions (SPADES)

      Geoffrey Foster, Jacobs Inc., Washington DC
      Tatyana Feygelson, Naval Research Laboratory
      James Gallagher, ASEE Postdoctoral Fellow Residing at NRL
      Josephine Chang, Northrop Grumman
      Shamima Afroz, Northrop Grumman
      Ken Nagamatsu, Northrop Grumman
      Robert Howell, Northrop Grumman
      Fritz Kub, Naval Research Laboratory

      The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

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  • Aktas, Ozgur

    QROMIS, USA
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Al-Mulla, Saoud

    University of Illinois, Urbana-Champaign
    • Transfer of Thin Film Gallium Phosphide onto Glass for Integrable Optical Filters

      Maanav Ganjoo, University of Illinois, Urbana-Champaign
      John Carlson, University of Illinois, Urbana-Champaign
      Saoud Al-Mulla, University of Illinois, Urbana-Champaign
      James Brown, University of Illinois, Urbana-Champaign
      Brian Cunningham, University of Illinois, Urbana-Champaign
      John Dallesasse, University of Illinois at Urbana-Chamapign

      A single-layer optical filter made from thin film gallium phosphide (GaP) is envisioned and a fabrication flow is outlined, with current progress on process development reported. Ion-implantation is simulated and performed on bulk GaP with He+, followed by a field-assisted thermal bonding technique that simultaneously bonds a thin GaP film onto a borofloat glass substrate and removes the GaP substrate. The resulting thin films have consistent thickness, both within and between runs, and RMS surface roughness of < 10 nm. Dry-etch processes that further reduce the thin film material are characterized and designs for etching gratings into them are developed. This process is shown to be a reliable means of creating thin films of consistent thickness and smoothness in GaP, for the purpose of establishing visible wavelength filters for spectroscopic applications.

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  • Almeida, Carlos

    Semilab SDI
    • Micro-scale Imaging of Electrical Activity of Yield Killer Defects in 4H-SiC with Charge Assisted KFM and UV-Photoluminescence

      Jacek Lagowski, Semilab SDI, Tampa, FL,
      Marshall Wilson, Semilab SDI, Tampa, FL,
      David Greenock, X-Fab
      Dmitriy Marinskiy, Semilab SDI, Tampa, FL,
      Alexandre Savtchouk, Semilab SDI
      Anthony Ross III, Semilab SDI
      Carlos Almeida, Semilab SDI
      Bret Schrayer, Semilab SDI, Tampa, FL,
      John D’Amico, Semilab SDI

      In this work we compare non-contact charge-voltage imaging and UV-photoluminescence (UV-PL) imaging of yield killer defects in epitaxial 4H-SiC wafers.  Two significant findings are based on macro- and micro-scale imaging, respectively.  1- Whole wafer images demonstrate that only a fraction of the UV-PL defects in triangular, downfall and carrot categories are electrically active. 2- Micro-scale images reveal similarities and differences between PL and electrical defect images.  Presented for the first time, micrometer resolution leakage patterns within triangular defects are consistent with the microstructure modeling in reference 1. The results imply that the depletion layer leakage within killer defects corresponds to exposed 3C-SiC polytypes. This leakage may be a consequence of the lower 2.2eV energy gap of 3C-SiC compared to 3.3eV in 4H-SiC.

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  • Amirifar, Nooshin

    imec
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Anderson, Travis J.

    U.S. Naval Research Laboratory
    • Exploring the capability of Hyperspectral Electroluminescence for process monitoring in vertical GaN devices

      Karl D. Hobart, U.S. Naval Research Laboratory
      Mona Ebrish, Vanderbilt University, Nashville, TN
      Travis J. Anderson, U.S. Naval Research Laboratory
      James Gallagher, U.S. Naval Research Laboratory
      Joseph Spencer, U.S. Naval Research Laboratory, Washington, DC, USA, Virginia Tech
      Jennifer Hite, U.S. Naval Research Laboratory
      Michael Mastro, U.S. Naval Research Laboratory

      GaN is a promising material for more efficient high frequency and high voltage power switching. However, GaN still is not the common material for power electronics due to immature substrate, homoepitaxial growth, and processing technology. Electroluminescence is a promising method to predict failure points due to high field stress, which can assist in the separation of inherent defects stemming from substrate quality, and from process-induced defects as well as identify problems related to proper edge termination design. In this work, we compare the Electroluminescence signatures of devices on inhomogeneous substrates to DC I-V behavior to demonstrate the utility of the technique for process monitoring.

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    • Predicting Vertical GaN Diode Quality using Long Range Optical tests on Substrates

      Francis Kub, U.S. Naval Research Laboratory
      James Gallagher, U.S. Naval Research Laboratory
      Andrew Koehler, Naval Research Laboratory
      Mona Ebrish, NRC Postdoc Fellow Residing at the U.S. Naval Research Laboratory
      Michael Mastro, U.S. Naval Research Laboratory
      Jennifer Hite, U.S. Naval Research Laboratory
      Karl Holbart, U.S. Naval Research Laboratory

      It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

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  • Ao, Jin-Ping

    The University of Tokushima
    • High Gate Voltage Swing Region of Normally-off p-GaN MIS-HEMT  With ALD-Growth Al2O3/AlN Gate Insulator Layer

      Jin-Ping Ao, The University of Tokushima
      Chi-Chuan Chiu, Chang Gung University

      Metal–insulator–semiconductor p-type GaN high-electron-mobility transistor with an Al2O3/AlN deposited by atomic layer deposition was investigated. The selected insulator, AlN has been proven to have a good interface with GaN. A traditional p-GaN device without an Al2O3/AlN layer was processed for comparison. Due to the Al2O3/AlN layer, the gate leakage was lower, and the threshold voltage was higher, at 4.7 V. Additionally, excellent turn-on voltage was obtained. Furthermore, low current degradation and smaller VTH shift at high temperatures was also observed. Hence, growing a good-quality Al2O3/AlN layer can achieve an enhancement-mode operation with superior stability and high gate swing region.

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  • Asel, Thaddeus

    Air Force Research Laboratory, Wright Patterson AFB, OH, USA
    • Self-Aligned Refractory Metal Gate Scaling in β-Ga2O3 MOSFETs

      Kelson Chabak, Air Force Research Laboratory, Sensors Directorate
      Kyle Liddy, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Andrew Green, Air Force Research Laboratory, Sensors Directorate
      Thaddeus Asel, Air Force Research Laboratory, Wright Patterson AFB, OH, USA
      Shin Mou, Air Force Research Laboratory, Wright Patterson AFB, OH
      Kevin Leedy, Air Force Research Laboratory, Sensors Directorate
      Donald Dorsey, Air Force Research Laboratory Materials and Manufacturing Directorate

      This work characterizes the effects of gate-length (LG) scaling in a self-aligned gate (SAG) β-Ga2O3 MOSFET process. Additional performance gains are expected by extending the SAG process from large LG to sub-micrometer dimensions.  This data incorporates LG scaling down to 200 nm to improve device performance in Ga2O3 SAG MOSFETs using a stepper lithography process to define sub-micron gate lengths.

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  • Bachman, Mark

    MACOM Technology Solutions
    • Laser Diode Junction Temperature Assessment for Reliability Optimization

      Malcolm Green, MACOM Technology Solutions
      Charles Recchia, MACOM Technology Solutions
      Mark Bachman, MACOM Technology Solutions
      Lihua Hu, MACOM Technology Solutions
      Wolfgang Parz, MACOM Technology Solutions

      Determination of reliability performance over time requires an accurate understanding of device junction temperature, not only in customer use condition, but also during production test and burn-in. Through carefully designed and executed LIV (L=Light, I=current, V=Voltage) measurements and a modeling framework where optical power, thermal and electrical device parameters are interrelated, the laser diode junction temperature, as confirmed by wavelength shift measurements, is obtained via regression of a non-linear self-consistent equation.  Modeled parameters include both threshold current and slope efficiency junction linear temperature dependence coefficients/constants, as well as a thermal impedance factor.

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  • Baclet, Stephanie

    Oxford Instruments Plasma Technology
    • High Uniformity Etching of GaAs/AlGaAs VCSEL Mesa

      Ligang Deng, Oxford Instruments Plasma Technology
      Katie Hore, Oxford Instruments Plasma Technology
      Ning Zhang, Oxford Instruments Plasma Technology
      Stephanie Baclet, Oxford Instruments Plasma Technology

      The etching of uniform, repeatable GaAs/AlGaAs mesas is an important step in manufacturing VCSELs. This paper presents a high uniformity, low foot etching of mesa structures on 6” wafers. The improved uniformity permits the use of production-friendly optical endpoint techniques which can be used to stop on a specific layer in the VCSEL structure.

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  • Bakeroot, Benoit

    imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Bakhtiary Noodeh, Marzieh

    Georgia Institute of Technology, Atlanta, GA
    • A Study of Low-Annealing-Temperature Ohmic Contact on n-Type GaN Layers

      Shyh-Chiang Shen, Georgia Institute of Technology
      Minkyu Cho, Georgia Institute of Technology, Atlanta, GA
      Marzieh Bakhtiary Noodeh, Georgia Institute of Technology, Atlanta, GA
      Theeradetch Detchprohm, Georgia Institute of Technology
      Russell Dupuis, Georgia Tech
      Barry Wu, Keysight Technologies, Inc.
      Don D’Avanzo, Keysight Technologies, Inc.

      Typical n-type ohmic contact formation for GaN material systems requires high-temperature thermal processes. The high-temperature process often leads to a rough surface after the annealing step. Low-annealing-ohmic contact is advantageous to prevent undesired surface roughening on the metal stack during this thermal process.  We report an approach to achieve low contact resistance on n-type GaN layers using a nitrogen plasma and a conventional Ti/Al-based metal stacks.  We observed an as-deposit ohmic contact behavior on the n-type contact with a specific contact resistance (rc,sp) in the mid-E-6 Ω∙cm2 range.  The rc,sp was further reduced to  6.8E-7 Ω∙cm2 after an annealing step at 600 oC.

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  • Barlage, Doug

    University of Alberta
    • Plasma Enhanced Atomic Layer Deposited Silicon Nitride on GaN MISCAPs with High Charge and Mobility

      Ken Cadien, University of Alberta
      Eric Milburn, University of Alberta
      Alex Ma, University of Alberta
      Gem Shoute, University of Alberta
      Doug Barlage, University of Alberta

      In this work fabrication of MISCAP structures was achieved on n-type gallium nitride using atomic layer deposited silicon nitride as the dielectric layer and sputtered ruthenium contacts. Preliminary values extracted from C-f data suggests very high capacitance densities up to 3.18 μF∙cm-2 and very high accumulation-mode field effect mobility, as high as 325 cm2V-1s-1 at a bias voltage of 2.5 V.

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  • Basceri, Cem

    QROMIS, USA
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Beam, Edward

    QORVO
    • Dispersion Characteristics of ScAlN and ScAlGaN HEMTs by Pulsed I-V Measurements

      Kelson Chabak., Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Cathy Lee, Qorvo Inc.
      Yu Cao, Raytheon IDS Microelectronics, Novati Technologies, Inc. IQE
      Andy Xie, Qorvo
      Edward Beam, QORVO
      Antonio Crespo, Air Force Research Laboratory, Sensors Directorate
      Dennis Walker, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Robert Fitch, AFRL
      James Gillespie, Air Force Research Laboratory
      Andrew Green, Air Force Research Laboratory, Sensors Directorate

      We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

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  • Beausoleil, Raymond

    Hewlett Packard Labs, Hewlett Packard Enterprise
    • Heterogenious Photonic Integration by Epitaxial regrowth on Wafer Bonded Substrates

      Raymond Beausoleil, Hewlett Packard Labs, Hewlett Packard Enterprise
      Yingtao Hu, Hewlett Packard Labs, Hewlett Packard Enterprise
      Di Liang, Hewlett Packard Labs, Hewlett Packard Enterprise
      Geza Kurczveil, Hewlett Packard Labs, Hewlett Packard Enterprise

      We present a novel heterogeneous photonic integration of III/V on silicon by using epitaxial regrowth on III/V-on-Si wafer bonded substrates. This integration method decouples the correlated root causes, i.e., lattice, thermal, and domain mismatches, which are all responsible for a large number of detrimental dislocations in the heteroepitaxial process.  The grown multi-quantum well vertical p–i–n diode laser structure shows a significantly low dislocation density of 9.5 × 104 cm−2, two orders of magnitude lower than the state-of-the-art conventional monolithic growth of III/V on Si. Hybrid InP-on-Si multi-quantum well lasers were successfully demonstrated with this heterogeneous integration and shown room-temperature pulsed and continuous-wave lasing. This generic concept can be applied to other material systems to provide higher integration density, more functionalities and lower total cost for photonics as well as microelectronics, MEMS, and many other applications.

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  • Ben-Slimane, Ahmed

    Yole Développement 75 cours Emile Zola, 69100 Villeurbanne France
    • Market opportunities for Wide-Band gap semiconductors in EV/HEV applications

      Ahmed Ben-Slimane, Yole Développement 75 cours Emile Zola, 69100 Villeurbanne France
      Hong LIN, Yole Développement 75 cours Emile Zola, 69100 Villeurbanne France
      Ezgi DOGMUS, Yole Développement

      The high growth of the EV/HEV market impacted significantly the wide bandgap semiconductor industry, creating new opportunities and a competition between SiC and GaN in many applications such as on-board chargers, DC-DC converters and main inverters. This paper provides an overview of SiC and GaN device technology, including Yole Développement’s understanding of the market’s current dynamics and future evolution of wide band gap materials compared to mainstream Silicon power electronics market.

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  • Ben-Slimane, Ahmed

    Yole Developpement
    • Impact of high volume 3D Sensing applications on Compound Semiconductor Industry

      Pierrick Boulay, Yole Developpement
      Hong LIN, Yole Developpement
      Ahmed Ben-Slimane, Yole Developpement
      Pars Mukish, Yole Developpement
      Ezgi DOGMUS, Yole Développement
  • Ben-Slimane, Ahmed

    Yole Developpement
    • 5G impact on Wireless Infrastructure and Compound Semiconductor Industry

      Ahmed Ben-Slimane, Yole Developpement
      Antoine Bonnabel, Yole Developpement
      Cédric MALAQUIN, Yole Developpement
      Claire Troadec, Yole Developpement
      Hong LIN, Yole Developpement
      Ezgi DOGMUS, Yole Développement

      The paper presents the market overview of different compound semiconductor such as GaN, GaAs, and InP impacted by the deployment of 5G in wireless infrastructure. The value chain from wafer and epitaxy to device level is covered, as well as technology and market trends and Yole’s forecast for the coming years.

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  • Bickel, Nicole

    Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
    • The influence of the GaN substrate types and the active area scaling design on the conduction properties of vertical GaN MISFETs for laser driving applications

      Joachim Würfl, Ferdinand-Braun-Institut, Berlin, Germany
      Eldad Bahat Treidel, Ferdinand-Braun-Institut, Berlin, Germany
      Oliver Hilt, Ferdinand-Braun-Institut (FBH)
      Veit Hoffman, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Frank Brunner, Ferdinand-Braun-Institut, Berlin, Germany
      Bernd Janke, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Nicole Bickel, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Hossein Yazdani, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Hassan Gargouri, SENTECH Instruments GmbH

      In this work we present a systematic study on the conduction properties in vertical GaN trench MISFETs grown and manufactured on different free standing GaN substrates. It is shown that devices manufactured on ammonothermal substrates have superior conduction current density higher than 4 kA/cm2, specific on‑state resistance as low as 1.1 ± 0.1 mWcm2 and channel sheet resistance of 19.6 ± 0.9 Wmm. It is further shown that scaling these devices to large gate periphery is not limited by current spreading in the drift region, low channel mobility or by self‑heating. The conduction properties of devices manufactured on ammonothermal GaN substrates are found to be the most suitable for pulsed laser driving applications.

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  • Birkhahn, Ron

    Transphorm Inc.
    • Manufacturing of N-polar GaN on Sapphire Epitaxial Wafers for Millimeter-wave Electronics Applications

      Umesh Mishra, Transphorm also Dean of Engineering UCSB
      Xiang Liu, Transphorm Inc.
      Ron Birkhahn, Transphorm Inc.
      Stacia Keller, Transphorm Inc.
      Brian Swenson, Transphorm Inc.
      Lee McCarthy, Transphorm Inc.
      Davide Bisi, Transphorm Inc.

      Transphorm is supplying N-polar GaN on SiC and sapphire epitaxial wafers for customers developing ultra-high performance RF and mm-wave electronics devices. The manufacturing process is SPC controlled and DOE optimized, and the wafers exhibit very high 2DEG electron mobility and excellent thickness and Rsh uniformities.

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  • Bisi, Davide

    Transphorm Inc.
    • Manufacturing of N-polar GaN on Sapphire Epitaxial Wafers for Millimeter-wave Electronics Applications

      Umesh Mishra, Transphorm also Dean of Engineering UCSB
      Xiang Liu, Transphorm Inc.
      Ron Birkhahn, Transphorm Inc.
      Stacia Keller, Transphorm Inc.
      Brian Swenson, Transphorm Inc.
      Lee McCarthy, Transphorm Inc.
      Davide Bisi, Transphorm Inc.

      Transphorm is supplying N-polar GaN on SiC and sapphire epitaxial wafers for customers developing ultra-high performance RF and mm-wave electronics devices. The manufacturing process is SPC controlled and DOE optimized, and the wafers exhibit very high 2DEG electron mobility and excellent thickness and Rsh uniformities.

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  • Blank, Volker

    LayTec AG
    • Advanced semiconductor metrology and process control using UV-A/UV-B LEDs

      Kolja Haberland, LayTec AG
      Kamau Prince, LayTec AG
      Volker Blank, LayTec AG
      Johannes Zettler, LayTec AG

      Traditional in-situ reflectometry sensing at blue (405 nm), red (630 nm) and NIR (950 nm) wavelengths cannot resolve variations in InAlGaN surface roughness or layer thickness with the precision necessary for effective in situ process control. LayTec has developed in situ reflectance metrology at 280 nm to address this need.

      We report successful application of in situ UV reflect-ometry and curvature, distinguishing between various phases of strain relaxation and surface relaxation during non-pseudomorphic growth of Al0.5Ga0.5N on AlN/sapphire. Results were validated by XRD, TEM and AFM. Results illuminate the influence of reduced TDD on relaxation effects during growth of UVA and UVB LED structures.

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  • Blevins, John

    Air Force Research Laboratory (AFRL), Wright-Patterson AFB, OH
    • Development of a World Class Silicon Carbide Substrate Manufacturing Capability

      John Blevins, Air Force Research Laboratory (AFRL), Wright-Patterson AFB, OH

      Silicon carbide (SiC) semiconductor substrates are the foundation for revolutionary improvements in the cost, size, weight and performance of a broad range of military and commercial radio frequency (RF) and power switching devices. Due to the lack of a viable, native gallium nitride (GaN) substrate, semi-insulating (SI) SiC substrates are presently the substrate of choice for high power AlGaN/GaN High Electron Mobility Transistors (HEMTs) due to their near lattice-match to GaN, superior thermal conductivity and commercial availability. GaN has emerged as the technology of choice for RF power because of its superior output power capability compared to gallium arsenide.  Similarly, semi-conducting (N+) SiC substrates are required for fabrication of high voltage Schottky diodes and metal oxide semiconductor field effect transistor (MOSFET) power switching devices. Critical to this realization is the availability of affordable, high quality, large diameter SI and N+ SiC substrates for production of GaN and SiC power semiconductors.  SiC is unique in that bulk single crystals cannot be grown via traditional melt-based manufacturing processes such as Czochralski. Rather, a high temperature sublimation process is required. In the late 1980s, pioneering physical vapor transport research taking place at North Carolina State University ultimately led to the formation of Cree Research and subsequently the wide bandgap semiconductor industry.  U.S. Department of Defense investment in wide bandgap semiconductors, since the early 1990s, has easily exceeded $1B spawning an entirely new industry. The early days of SiC physical vapor transport growth research were fraught with perceived insurmountable technical challenges associated with micropipes, doping, polytype conversion, diameter expansion and crystalline defects. Despite this monumental crystal growth, technology hurdles, SiC substrates are presently manufactured at a cost and quality never thought possible. This paper highlights more than 20 years of AFRL sponsored development with II-VI aimed at positioning itself as a world-class manufacturer of SiC substrates.

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  • Bolognesi, Colombo

    ETH-Zurich
    • Gate Recess Etch Sensitivity of Thick and Highly-Doped GaInAs Cap Layer in InP HEMT Fabrication

      Colombo Bolognesi, ETH-Zurich
      Daxin Han, ETH-Zürich
      Diego Calvo Ruiz, ETH-Zürich
      Tamara Saranovac, ETH-Zurich
      Olivier Ostinelli, ETH-Zurich

      The use of highly-doped thick cap layers is a common strategy to enhance the performance of GaInAs/AlInAs/InP High Electron Mobility Transistors (HEMTs) by reducing the Ohmic contact resistance (RC). However, because of the high doping level, cap layers become very sensitive to processing steps performed before and during gate recess etching. In this paper, the sensitivity of gate recess etching on a 20 nm highly-doped GaInAs cap layer (doped 7.3 × 1019 cm-3) is studied with respect to Ohmic contact type (annealed/non-annealed), chip size, gate finger length, and etchant choice. The use of very high cap doping levels exacerbates device and process scaling challenges. For example, the recess finger length dependence complicates multi-project wafer runs which would simultaneously include narrow finger HEMTs used in digital ICs and longer finger HEMTs used in microwave analog circuits.

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  • Bonnabel, Antoine

    Yole Developpement
    • 5G impact on Wireless Infrastructure and Compound Semiconductor Industry

      Ahmed Ben-Slimane, Yole Developpement
      Antoine Bonnabel, Yole Developpement
      Cédric MALAQUIN, Yole Developpement
      Claire Troadec, Yole Developpement
      Hong LIN, Yole Developpement
      Ezgi DOGMUS, Yole Développement

      The paper presents the market overview of different compound semiconductor such as GaN, GaAs, and InP impacted by the deployment of 5G in wireless infrastructure. The value chain from wafer and epitaxy to device level is covered, as well as technology and market trends and Yole’s forecast for the coming years.

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  • Boulay, Pierrick

    Yole Developpement
    • Impact of high volume 3D Sensing applications on Compound Semiconductor Industry

      Pierrick Boulay, Yole Developpement
      Hong LIN, Yole Developpement
      Ahmed Ben-Slimane, Yole Developpement
      Pars Mukish, Yole Developpement
      Ezgi DOGMUS, Yole Développement
  • Brown, David

    HRL Laboratories, LLC.
    • 140 nm and 90 nm GaN MMIC Technology for Millimeter-wave Power Applications

      Jose Diaz, BAE Systems Inc
      David Brown, HRL Laboratories, LLC.
      Carlton Creamer, BAE Systems Inc
      Kanin Chu, BAE Systems Inc
      Richard Isaak, BAE Systems Inc
      Louis Mt. Pleasant, BAE Systems Inc
      Donald Mitchell, BAE Systems Inc
      Puneet Srivastava, BAE Systems Inc
      Wen Zhu, BAE Systems Inc
      Hong Lu, BAE Systems Inc

      This work describes an on-going effort to develop and mature a 140 nm GaN MMIC technology with a focus on efficient power amplification at frequencies ranging from DC to 50 GHz and a 90 nm technology targeted towards V- and W-band applications, and then release the technologies within a foundry process that is open to the DoD community.

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  • Brown, James

    University of Illinois, Urbana-Champaign
    • Transfer of Thin Film Gallium Phosphide onto Glass for Integrable Optical Filters

      Maanav Ganjoo, University of Illinois, Urbana-Champaign
      John Carlson, University of Illinois, Urbana-Champaign
      Saoud Al-Mulla, University of Illinois, Urbana-Champaign
      James Brown, University of Illinois, Urbana-Champaign
      Brian Cunningham, University of Illinois, Urbana-Champaign
      John Dallesasse, University of Illinois at Urbana-Chamapign

      A single-layer optical filter made from thin film gallium phosphide (GaP) is envisioned and a fabrication flow is outlined, with current progress on process development reported. Ion-implantation is simulated and performed on bulk GaP with He+, followed by a field-assisted thermal bonding technique that simultaneously bonds a thin GaP film onto a borofloat glass substrate and removes the GaP substrate. The resulting thin films have consistent thickness, both within and between runs, and RMS surface roughness of < 10 nm. Dry-etch processes that further reduce the thin film material are characterized and designs for etching gratings into them are developed. This process is shown to be a reliable means of creating thin films of consistent thickness and smoothness in GaP, for the purpose of establishing visible wavelength filters for spectroscopic applications.

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  • Brunner, Frank

    Ferdinand-Braun-Institut, Berlin, Germany
    • The influence of the GaN substrate types and the active area scaling design on the conduction properties of vertical GaN MISFETs for laser driving applications

      Joachim Würfl, Ferdinand-Braun-Institut, Berlin, Germany
      Eldad Bahat Treidel, Ferdinand-Braun-Institut, Berlin, Germany
      Oliver Hilt, Ferdinand-Braun-Institut (FBH)
      Veit Hoffman, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Frank Brunner, Ferdinand-Braun-Institut, Berlin, Germany
      Bernd Janke, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Nicole Bickel, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Hossein Yazdani, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Hassan Gargouri, SENTECH Instruments GmbH

      In this work we present a systematic study on the conduction properties in vertical GaN trench MISFETs grown and manufactured on different free standing GaN substrates. It is shown that devices manufactured on ammonothermal substrates have superior conduction current density higher than 4 kA/cm2, specific on‑state resistance as low as 1.1 ± 0.1 mWcm2 and channel sheet resistance of 19.6 ± 0.9 Wmm. It is further shown that scaling these devices to large gate periphery is not limited by current spreading in the drift region, low channel mobility or by self‑heating. The conduction properties of devices manufactured on ammonothermal GaN substrates are found to be the most suitable for pulsed laser driving applications.

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  • Bubber, Randhir

    Veeco Instruments
    • InAlN HEMT Epi and RF Devices on 8”-Si

      Huili Xing, Cornell University
      Ming Pan, Veeco Instruments
      Soo-Min Lee, Veeco Instruments
      Eric Tucker, Veeco Instruments
      Randhir Bubber, Veeco Instruments
      Ajit Paranjpe, Veeco Instruments
      Drew Hanser, Veeco Instruments, Inc.
      Kazuki Nomoto, Cornell University
      Lei Li, Cornell University
      Debdeep Jena, Cornell University

      In this paper, we report our work on epitaxial growth of InAlN HEMTs for RF device applications.  InAlN HEMTs were grown on 8” high resistivity silicon substrates. Various characterization techniques were used to analyze the quality of the epi wafers. An average sheet resistance (Rsh) of 206Ω/□, with a uniformity of 1.5% (1s/average), indicated a high quality and uniform 2DEG. Hall measurement showed a high sheet charge density of 2.27×1013cm−2 and a mobility of 1430cm2/(Vs). A pit free epi surface was obtained with optimized growth process of the active layers. T-gate RF devices fabricated on the InAlN epi wafers demonstrated an fT of 250GHz and an fMAX of 204 GHz, which are the record high values for GaN-based HEMTs on silicon.

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  • Burke, Edmund

    Skyworks Solutions, Inc.
    • The Effect of Delay Between Pre-clean and Metal Deposition on the Forward Current Voltage Characteristics of Schottky Devices

      Eric Finchem, MACOM
      Debdas Pal, MACOM
      Lorain Ross, Skyworks Solutions, Inc.
      Sean Doonan, Skyworks Solutions, Inc.
      Edmund Burke, Skyworks Solutions, Inc.

      Schottky devices play an important role in modern electronics. The forward biased current-voltage characteristics of such devices are linear on a semi-logarithm scale at intermediate bias voltages. However, the curve deviates from linearity at higher voltage primarily due to series resistance. The applied forward voltage on the device is equal to the sum of the voltage drops across the (1) junction, (2) series resistance, (3) depletion layer and (4) any parasitic resistive layer between the Schottky metal and the semiconductor. Therefore, the interface between the metal and the semiconductor plays an important role in determining the critical parameters of Schottky devices. In this investigation a controlled delay was introduced between the pre-metal clean and Schottky metal deposition steps of the fabrication process to study the effects of naturally grown oxide on the forward characteristics of the Schottky devices.  The results of the investigation indicate such delays cause significant increases in series resistance and ideality factor, as well as a decrease in barrier height.

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  • Bytheway, Richard

    Bruker UK Ltd
    • Correlation study between molten KOH etching and laboratory X-ray Diffraction Imaging (X-ray topography) in n+ 4H-SiC wafers

      David Jacques, Bruker UK Ltd
      Vishal Shah, University of Warwick
      Richard Bytheway, Bruker UK Ltd
      Tamzin Lafford, Bruker UK Ltd
      Benjamin Renz, University of Warwick
      Peter Gammon, University of Warwick
      Paul Ryan, Bruker UK Ltd
      Hrishikesh Das, ON Semiconductor

      In order to meet the forecast growing demand of n+ SiC material, wafer suppliers will need to implement new metrology techniques to allow the detection of crystalline defects and ensure the quality of their materials. Incumbent techniques such as KOH etching have been used for many years but remain very costly as the wafers cannot be processed further. Alternative techniques such as X-ray Diffraction Imaging (X-ray Topography) can be used to detect crystalline defects non-destructively but studies have been limited to synchrotron radiation which cannot be used as an in-line characterization. In this paper, Bruker have used novel equipment (Sensus-CS) to study the correlation between laboratory X-ray Diffraction Imaging and KOH etching performed at the University of Warwick.

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  • Cadien, Ken

    University of Alberta
    • Plasma Enhanced Atomic Layer Deposited Silicon Nitride on GaN MISCAPs with High Charge and Mobility

      Ken Cadien, University of Alberta
      Eric Milburn, University of Alberta
      Alex Ma, University of Alberta
      Gem Shoute, University of Alberta
      Doug Barlage, University of Alberta

      In this work fabrication of MISCAP structures was achieved on n-type gallium nitride using atomic layer deposited silicon nitride as the dielectric layer and sputtered ruthenium contacts. Preliminary values extracted from C-f data suggests very high capacitance densities up to 3.18 μF∙cm-2 and very high accumulation-mode field effect mobility, as high as 325 cm2V-1s-1 at a bias voltage of 2.5 V.

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  • Calvo Ruiz, Diego

    ETH-Zürich
    • Gate Recess Etch Sensitivity of Thick and Highly-Doped GaInAs Cap Layer in InP HEMT Fabrication

      Colombo Bolognesi, ETH-Zurich
      Daxin Han, ETH-Zürich
      Diego Calvo Ruiz, ETH-Zürich
      Tamara Saranovac, ETH-Zurich
      Olivier Ostinelli, ETH-Zurich

      The use of highly-doped thick cap layers is a common strategy to enhance the performance of GaInAs/AlInAs/InP High Electron Mobility Transistors (HEMTs) by reducing the Ohmic contact resistance (RC). However, because of the high doping level, cap layers become very sensitive to processing steps performed before and during gate recess etching. In this paper, the sensitivity of gate recess etching on a 20 nm highly-doped GaInAs cap layer (doped 7.3 × 1019 cm-3) is studied with respect to Ohmic contact type (annealed/non-annealed), chip size, gate finger length, and etchant choice. The use of very high cap doping levels exacerbates device and process scaling challenges. For example, the recess finger length dependence complicates multi-project wafer runs which would simultaneously include narrow finger HEMTs used in digital ICs and longer finger HEMTs used in microwave analog circuits.

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  • Cao, Lina

    Keysight Technologies
    • RF Harmonic Distortion of Coplanar Waveguides on GaN-on-Si and GaN-on-SiC Substrates

      Patrick Fay, University of Notre Dame
      Lina Cao, Keysight Technologies
      Hansheng Ye, University of Notre Dame
      Jingshan Wang, Notre Dame
      Hugues Marchand, IQE
      Wayne Johnson, IQE

      The RF harmonic distortion of coplanar waveguides (CPWs) fabricated on AlGaN/GaN HEMT heterostructures grown on both high-resistivity Si (GaN-on-Si) and semi-insulating SiC (GaN-on-SiC) substrates is reported for the first time. The loss performance and the nonlinear behavior of the CPW lines were experimentally characterized using both small- and large-signal measurements. From 100 MHz to 20 GHz, low loss (less than 0.3 dB/mm at 20 GHz) was achieved; the attenuation of CPW lines on the GaN-on-Si substrate is ~0.05 dB/mm higher than that of the GaN-on-SiC substrate. The harmonic distortion levels of the GaN-on-Si substrate and GaN-on-SiC were also evaluated experimentally; in contrast to the small-signal loss, more significant differences in second- and third-order nonlinearity, and thus intermodulation, are observed between Si and SiC substrates. Large-signal characterization of the GaN-on-Si substrate was carried out over temperature from 25 °C to 175 °C.  Due to increases in substrate conductivity with temperature, the harmonic distortion levels are found to increase significantly at temperatures above 75 °C.

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  • Cao, Yu

    Raytheon IDS Microelectronics, Novati Technologies, Inc. IQE
    • Dispersion Characteristics of ScAlN and ScAlGaN HEMTs by Pulsed I-V Measurements

      Kelson Chabak., Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Cathy Lee, Qorvo Inc.
      Yu Cao, Raytheon IDS Microelectronics, Novati Technologies, Inc. IQE
      Andy Xie, Qorvo
      Edward Beam, QORVO
      Antonio Crespo, Air Force Research Laboratory, Sensors Directorate
      Dennis Walker, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Robert Fitch, AFRL
      James Gillespie, Air Force Research Laboratory
      Andrew Green, Air Force Research Laboratory, Sensors Directorate

      We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

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  • Carlson, John

    University of Illinois, Urbana-Champaign
    • Transfer of Thin Film Gallium Phosphide onto Glass for Integrable Optical Filters

      Maanav Ganjoo, University of Illinois, Urbana-Champaign
      John Carlson, University of Illinois, Urbana-Champaign
      Saoud Al-Mulla, University of Illinois, Urbana-Champaign
      James Brown, University of Illinois, Urbana-Champaign
      Brian Cunningham, University of Illinois, Urbana-Champaign
      John Dallesasse, University of Illinois at Urbana-Chamapign

      A single-layer optical filter made from thin film gallium phosphide (GaP) is envisioned and a fabrication flow is outlined, with current progress on process development reported. Ion-implantation is simulated and performed on bulk GaP with He+, followed by a field-assisted thermal bonding technique that simultaneously bonds a thin GaP film onto a borofloat glass substrate and removes the GaP substrate. The resulting thin films have consistent thickness, both within and between runs, and RMS surface roughness of < 10 nm. Dry-etch processes that further reduce the thin film material are characterized and designs for etching gratings into them are developed. This process is shown to be a reliable means of creating thin films of consistent thickness and smoothness in GaP, for the purpose of establishing visible wavelength filters for spectroscopic applications.

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  • Chabak, Kelson

    Air Force Research Laboratory, Sensors Directorate
    • Self-Aligned Refractory Metal Gate Scaling in β-Ga2O3 MOSFETs

      Kelson Chabak, Air Force Research Laboratory, Sensors Directorate
      Kyle Liddy, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Andrew Green, Air Force Research Laboratory, Sensors Directorate
      Thaddeus Asel, Air Force Research Laboratory, Wright Patterson AFB, OH, USA
      Shin Mou, Air Force Research Laboratory, Wright Patterson AFB, OH
      Kevin Leedy, Air Force Research Laboratory, Sensors Directorate
      Donald Dorsey, Air Force Research Laboratory Materials and Manufacturing Directorate

      This work characterizes the effects of gate-length (LG) scaling in a self-aligned gate (SAG) β-Ga2O3 MOSFET process. Additional performance gains are expected by extending the SAG process from large LG to sub-micrometer dimensions.  This data incorporates LG scaling down to 200 nm to improve device performance in Ga2O3 SAG MOSFETs using a stepper lithography process to define sub-micron gate lengths.

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  • Chabak., Kelson

    Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
    • Dispersion Characteristics of ScAlN and ScAlGaN HEMTs by Pulsed I-V Measurements

      Kelson Chabak., Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Cathy Lee, Qorvo Inc.
      Yu Cao, Raytheon IDS Microelectronics, Novati Technologies, Inc. IQE
      Andy Xie, Qorvo
      Edward Beam, QORVO
      Antonio Crespo, Air Force Research Laboratory, Sensors Directorate
      Dennis Walker, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Robert Fitch, AFRL
      James Gillespie, Air Force Research Laboratory
      Andrew Green, Air Force Research Laboratory, Sensors Directorate

      We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

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  • Chang, Josephine

    Northrop Grumman
    • Formation of Diamond Superjunctions to Enable GaN-Based Super-Lattice Power Amplifiers with Diamond Enhanced Superjunctions (SPADES)

      Geoffrey Foster, Jacobs Inc., Washington DC
      Tatyana Feygelson, Naval Research Laboratory
      James Gallagher, ASEE Postdoctoral Fellow Residing at NRL
      Josephine Chang, Northrop Grumman
      Shamima Afroz, Northrop Grumman
      Ken Nagamatsu, Northrop Grumman
      Robert Howell, Northrop Grumman
      Fritz Kub, Naval Research Laboratory

      The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

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  • Chang, Josephine

    Northrop Grumman Mission Systems
    • Productization of the Superlattice Castellated Field Effect Transistor

      Justin Parke, Northrop Grumman Mission Systems
      I. Wathuthanthri, Northrop Grumman (MS), Linthicum, MD
      Ken Nagamatsu, Northrop Grumman Mission Systems
      Josephine Chang, Northrop Grumman Mission Systems
      Georges Siddiqi, HRL Laboratories
      R. Lewis, Northrop Grumman (MS), Linthicum, MD
      Robert Howell, Northrop Grumman Mission Systems

      NGMS reports the maturation of a novel GaN based 3D transistor with state of the art RF switch performance, named the SLCFET (Super Lattice Castellated Field Effect Transistor), with an RF switch FOM greater than 1.8 THz. The configured process has undergone reliability qualification for production.

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  • Chang, Josephine

    Northrop Grumman Corporation
    • 100nm, Three-dimensional T-Gate for SLCFET Amplifiers

      Robert Howell, Northrop Grumman Corporation
      Annaliese Drechsler, Northrop Grumman (MS), Linthicum, MD
      Ken Nagamatsu, Northrop Grumman Corporation
      Kevin Frey, Northrop Grumman Corporation
      Monique Farrell, Northrop Grumman Corporation
      Georges Siddiqi, HRL Laboratories
      M. Scimonelli, Northrop Grumman (MS), Linthicum, MD
      Jordan Merkle, Northrop Grumman Corporation
      Josephine Chang, Northrop Grumman Corporation

      This report describes the first demonstration of a 100nm T-gate for the Superlattice Castellation Field Effect Transistor (SLCFET) amplifier. The SLCFET amplifier device utilizes a superlattice of GaN/AlGaN channels, which enables a high charge density and low source resistance. A three-dimensional T-gate structure provides electrostatic control of the channels while maintaining high gain. Improvements to the T-gate process have allowed for the scaling of the gate down to 100nm while maintaining excellent gate control, with an on to off current ratio exceeding 107. This gate scaling allows the device to reach FT / FMAX of 70/110 GHz with full passivation to maintain compatibility with the productionized SLCFET switch process.

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  • Chen, Szu-Ting

    WIN Semiconductors Corp.
    • AlGaN/GaN Ohmic Contact Investigation

      Kai-Sin Cho, WIN Semiconductors Corp.
      Chiao-Yi Tsai, WIN Semiconductors Corp.
      Szu-Ting Chen, WIN Semiconductors Corp.
      Cheng-Ju Lin, WIN Semiconductors Corp.
      Yi-Wei Lien, WIN Semiconductors Corp
      Wei-Chou Wang, WIN Semiconductors Corp

      To produce high performance AlGaN/GaN heterostructure field effect transistors for RF power applications, one of the critical control parameters of AlGaN/GaN system is the contact resistance (Rc) of the ohmic metal to AlGaN. In the present study, two important factors for the contact resistance, a Ti3AlN interfacial layer and TiN islands were investigated using phase identification, and morphology as determined by Nano Beam Electron Diffraction (NBD) technique in transmission electron microscopy. Based on our study, both Ti3AlN interfacial layer and TiN islands contribute to ohmic contact behavior in the system.

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  • Chiu, Chao-Wei

    Chang Gung University
    • The Improvement of Mg Out-diffusion in Normally-off p-GaN Gate HEMT Using Pulsed Laser Activation Technique

      Chong Rong Haung, Chang Gung University
      Hsiang-Chun Wang, Chang Gung University
      Chao-Wei Chiu, Chang Gung University

      A low- Magnesium (Mg) out-diffusion normally off p-GaN gated AlGaN/GaN high-electron-mobility transistor (HEMT) was developed using a low-temperature laser activation technique. Conventionally, during the actual p-GaN layer activation procedure, Mg out-diffuses into the AlGaN barrier and GaN channel at high temperatures. In addition, the Al of the AlGaN barrier layer is injected into GaN to generate alloy scattering and to suppress current density. In this study, the GaN doped Mg layer (Mg:GaN)was activated using short-wavelength Nd:YAG pulse laser annealing, and a conventional thermal activation device was processed for comparison. The results demonstrated that the laser activation technique in p-GaN HEMT suppressed the Mg out-diffusion-induced leakage current and trapping effect and enhanced the current density and breakdown voltage. Therefore, using this novel technique, a high and active Mg concentration and a favorable doping confinement can be obtained in the p-GaN layer to realize a stable enhancement-mode operation.

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    • The Characteristics of 6-inch GaN on Si RF HEMT with High Isolation Composited Buffer Layer Design

      Chong Rong Huang, Chang Gung University

      In this study, a 50-nm Al0.05Ga0.95N back barrier (BB) layer was used in an AlGaN/GaN high-electron-mobility transistor between the two-dimensional electron gas channel and Fe-doped/C-doped buffer layers. This BB layer can reduce the channel layer. The BB layer is affected by doped carriers in the buffer layer and the conduction energy band between the channel and the buffer layers. The Ion/Ioff ratio of the BB device was 3.43 × 105 and the ratio for the device without BB was 1.91 × 103. Lower leakage currents were obtained in the BB device because of the higher conduction energy band. The 0.25-μm gate length device with the BB exhibited a high current gain cutoff frequency of 26.9 GHz and power gain cutoff frequency of 54.7 GHz.

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    • High Gate Voltage Swing Region of Normally-off p-GaN MIS-HEMT  With ALD-Growth Al2O3/AlN Gate Insulator Layer

      Jin-Ping Ao, The University of Tokushima
      Chi-Chuan Chiu, Chang Gung University

      Metal–insulator–semiconductor p-type GaN high-electron-mobility transistor with an Al2O3/AlN deposited by atomic layer deposition was investigated. The selected insulator, AlN has been proven to have a good interface with GaN. A traditional p-GaN device without an Al2O3/AlN layer was processed for comparison. Due to the Al2O3/AlN layer, the gate leakage was lower, and the threshold voltage was higher, at 4.7 V. Additionally, excellent turn-on voltage was obtained. Furthermore, low current degradation and smaller VTH shift at high temperatures was also observed. Hence, growing a good-quality Al2O3/AlN layer can achieve an enhancement-mode operation with superior stability and high gate swing region.

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    • The Impact of AlxGa1-xN Back Barrier in AlGaN/GaN High Electron Mobility Transistors (HEMTs) on 6-inch MCZ Si Substrate

      Yen-Lun Huang
      Hsien-Chin Chiu, Chang Gung University
      H.Y. Wang, Chang Gung University
      Chia-Hao Liu, Chang Gung University
      WEN-CHING HSU
      CHE-MING LIU
      CHIH-YUAN CHUANG
      JIA-ZHE LIU

      In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al0.08GaN) of the B.B. more strongly affected the device’ Ion/Ioff ratio. It exhibited a low leakage current and high Ion/Ioff ratio of approximately 106. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic RON. The current gain cut-off frequency (fT) and maximum stable gain cut-off frequency (fmax) were 5.2 GHz and 10.5 GHz, respectively, for the Al0.08GaN B.B. device.

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  • Chiu, Chi-Chuan

    Chang Gung University
    • High Gate Voltage Swing Region of Normally-off p-GaN MIS-HEMT  With ALD-Growth Al2O3/AlN Gate Insulator Layer

      Jin-Ping Ao, The University of Tokushima
      Chi-Chuan Chiu, Chang Gung University

      Metal–insulator–semiconductor p-type GaN high-electron-mobility transistor with an Al2O3/AlN deposited by atomic layer deposition was investigated. The selected insulator, AlN has been proven to have a good interface with GaN. A traditional p-GaN device without an Al2O3/AlN layer was processed for comparison. Due to the Al2O3/AlN layer, the gate leakage was lower, and the threshold voltage was higher, at 4.7 V. Additionally, excellent turn-on voltage was obtained. Furthermore, low current degradation and smaller VTH shift at high temperatures was also observed. Hence, growing a good-quality Al2O3/AlN layer can achieve an enhancement-mode operation with superior stability and high gate swing region.

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  • Chiu, Hsien-Chin

    Chang Gung University
    • The Impact of AlxGa1-xN Back Barrier in AlGaN/GaN High Electron Mobility Transistors (HEMTs) on 6-inch MCZ Si Substrate

      Yen-Lun Huang
      Hsien-Chin Chiu, Chang Gung University
      H.Y. Wang, Chang Gung University
      Chia-Hao Liu, Chang Gung University
      WEN-CHING HSU
      CHE-MING LIU
      CHIH-YUAN CHUANG
      JIA-ZHE LIU

      In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al0.08GaN) of the B.B. more strongly affected the device’ Ion/Ioff ratio. It exhibited a low leakage current and high Ion/Ioff ratio of approximately 106. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic RON. The current gain cut-off frequency (fT) and maximum stable gain cut-off frequency (fmax) were 5.2 GHz and 10.5 GHz, respectively, for the Al0.08GaN B.B. device.

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    • High Gate Voltage Swing Region of Normally-off p-GaN MIS-HEMT  With ALD-Growth Al2O3/AlN Gate Insulator Layer

      Jin-Ping Ao, The University of Tokushima
      Chi-Chuan Chiu, Chang Gung University

      Metal–insulator–semiconductor p-type GaN high-electron-mobility transistor with an Al2O3/AlN deposited by atomic layer deposition was investigated. The selected insulator, AlN has been proven to have a good interface with GaN. A traditional p-GaN device without an Al2O3/AlN layer was processed for comparison. Due to the Al2O3/AlN layer, the gate leakage was lower, and the threshold voltage was higher, at 4.7 V. Additionally, excellent turn-on voltage was obtained. Furthermore, low current degradation and smaller VTH shift at high temperatures was also observed. Hence, growing a good-quality Al2O3/AlN layer can achieve an enhancement-mode operation with superior stability and high gate swing region.

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    • The Improvement of Mg Out-diffusion in Normally-off p-GaN Gate HEMT Using Pulsed Laser Activation Technique

      Chong Rong Haung, Chang Gung University
      Hsiang-Chun Wang, Chang Gung University
      Chao-Wei Chiu, Chang Gung University

      A low- Magnesium (Mg) out-diffusion normally off p-GaN gated AlGaN/GaN high-electron-mobility transistor (HEMT) was developed using a low-temperature laser activation technique. Conventionally, during the actual p-GaN layer activation procedure, Mg out-diffuses into the AlGaN barrier and GaN channel at high temperatures. In addition, the Al of the AlGaN barrier layer is injected into GaN to generate alloy scattering and to suppress current density. In this study, the GaN doped Mg layer (Mg:GaN)was activated using short-wavelength Nd:YAG pulse laser annealing, and a conventional thermal activation device was processed for comparison. The results demonstrated that the laser activation technique in p-GaN HEMT suppressed the Mg out-diffusion-induced leakage current and trapping effect and enhanced the current density and breakdown voltage. Therefore, using this novel technique, a high and active Mg concentration and a favorable doping confinement can be obtained in the p-GaN layer to realize a stable enhancement-mode operation.

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  • Cho, Kai-Sin

    WIN Semiconductors Corp.
    • AlGaN/GaN Ohmic Contact Investigation

      Kai-Sin Cho, WIN Semiconductors Corp.
      Chiao-Yi Tsai, WIN Semiconductors Corp.
      Szu-Ting Chen, WIN Semiconductors Corp.
      Cheng-Ju Lin, WIN Semiconductors Corp.
      Yi-Wei Lien, WIN Semiconductors Corp
      Wei-Chou Wang, WIN Semiconductors Corp

      To produce high performance AlGaN/GaN heterostructure field effect transistors for RF power applications, one of the critical control parameters of AlGaN/GaN system is the contact resistance (Rc) of the ohmic metal to AlGaN. In the present study, two important factors for the contact resistance, a Ti3AlN interfacial layer and TiN islands were investigated using phase identification, and morphology as determined by Nano Beam Electron Diffraction (NBD) technique in transmission electron microscopy. Based on our study, both Ti3AlN interfacial layer and TiN islands contribute to ohmic contact behavior in the system.

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  • Cho, Minkyu

    Georgia Institute of Technology, Atlanta, GA
    • A Study of Low-Annealing-Temperature Ohmic Contact on n-Type GaN Layers

      Shyh-Chiang Shen, Georgia Institute of Technology
      Minkyu Cho, Georgia Institute of Technology, Atlanta, GA
      Marzieh Bakhtiary Noodeh, Georgia Institute of Technology, Atlanta, GA
      Theeradetch Detchprohm, Georgia Institute of Technology
      Russell Dupuis, Georgia Tech
      Barry Wu, Keysight Technologies, Inc.
      Don D’Avanzo, Keysight Technologies, Inc.

      Typical n-type ohmic contact formation for GaN material systems requires high-temperature thermal processes. The high-temperature process often leads to a rough surface after the annealing step. Low-annealing-ohmic contact is advantageous to prevent undesired surface roughening on the metal stack during this thermal process.  We report an approach to achieve low contact resistance on n-type GaN layers using a nitrogen plasma and a conventional Ti/Al-based metal stacks.  We observed an as-deposit ohmic contact behavior on the n-type contact with a specific contact resistance (rc,sp) in the mid-E-6 Ω∙cm2 range.  The rc,sp was further reduced to  6.8E-7 Ω∙cm2 after an annealing step at 600 oC.

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  • Chochol, Jan

    ON Semiconductor CZ
    • P-type and N-type Channeling Ion Implantation of SiC and Implications for Device Design and Fabrication

      Takashi Kuroi, Nissin Ion Equipment Inc.
      Hrishikesh Das, ON Semiconductor USA
      Swapna Sunkari, ON Semiconductor USA
      Joshua Justice, ON Semiconductor USA
      Roman Malousek, ON Semiconductor CZ
      Jan Chochol, ON Semiconductor CZ
      Ryota Wada, Nissin Ion Equipment Inc.

      This work focuses on evaluating and demonstrating channeled p-type and n-type implantations in silicon carbide in a repeatable mass-production environment. Range increase of about 3X is observed using channeled conditions as opposed to normal incident conditions for both Aluminum and Phosphorous. The various advantages enabled by this technology for advanced device designs are highlighted. Super-junction devices targeting the same voltage range can be fabricated using 1 or 2 lesser epitaxial regrowth layers.

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  • choi, Chulsoon

    Wavice Inc.
    • Qualification of Wavice Baseline GaN HEMT process with 0.4 um gate on 4” SiC wafers

      Hosang Kwon, Agency for Defense Development
      Sangmin Lee, Wavice Inc.
      Byoungchul Jun, Wavice Inc.
      Chulsoon choi, Wavice Inc.
      Hyeyoung Jung, Wavice Inc.
      Seokgyu Choi, Wavice Inc.
      Min Han, Wavice Inc.
      Ho Geun Lee, Wavice Inc.
      Myoungkeun Song, Wavice Inc.
      Sung Won Lee, Wavice Inc.
      Young Jae Kim, Wavice Inc.
      Jihun Kwon, Wavice Inc.
      Myoungsoo Park, Wavice Inc.
      Sewon Hwang, Wavice Inc.
      Hangyol Ji, Wavice Inc.

      The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

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  • Choi, Seokgyu

    Wavice Inc.
    • Qualification of Wavice Baseline GaN HEMT process with 0.4 um gate on 4” SiC wafers

      Hosang Kwon, Agency for Defense Development
      Sangmin Lee, Wavice Inc.
      Byoungchul Jun, Wavice Inc.
      Chulsoon choi, Wavice Inc.
      Hyeyoung Jung, Wavice Inc.
      Seokgyu Choi, Wavice Inc.
      Min Han, Wavice Inc.
      Ho Geun Lee, Wavice Inc.
      Myoungkeun Song, Wavice Inc.
      Sung Won Lee, Wavice Inc.
      Young Jae Kim, Wavice Inc.
      Jihun Kwon, Wavice Inc.
      Myoungsoo Park, Wavice Inc.
      Sewon Hwang, Wavice Inc.
      Hangyol Ji, Wavice Inc.

      The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

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  • Chu, Kanin

    BAE Systems Inc
    • 140 nm and 90 nm GaN MMIC Technology for Millimeter-wave Power Applications

      Jose Diaz, BAE Systems Inc
      David Brown, HRL Laboratories, LLC.
      Carlton Creamer, BAE Systems Inc
      Kanin Chu, BAE Systems Inc
      Richard Isaak, BAE Systems Inc
      Louis Mt. Pleasant, BAE Systems Inc
      Donald Mitchell, BAE Systems Inc
      Puneet Srivastava, BAE Systems Inc
      Wen Zhu, BAE Systems Inc
      Hong Lu, BAE Systems Inc

      This work describes an on-going effort to develop and mature a 140 nm GaN MMIC technology with a focus on efficient power amplification at frequencies ranging from DC to 50 GHz and a 90 nm technology targeted towards V- and W-band applications, and then release the technologies within a foundry process that is open to the DoD community.

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  • CHUANG, CHIH-YUAN

    • The Impact of AlxGa1-xN Back Barrier in AlGaN/GaN High Electron Mobility Transistors (HEMTs) on 6-inch MCZ Si Substrate

      Yen-Lun Huang
      Hsien-Chin Chiu, Chang Gung University
      H.Y. Wang, Chang Gung University
      Chia-Hao Liu, Chang Gung University
      WEN-CHING HSU
      CHE-MING LIU
      CHIH-YUAN CHUANG
      JIA-ZHE LIU

      In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al0.08GaN) of the B.B. more strongly affected the device’ Ion/Ioff ratio. It exhibited a low leakage current and high Ion/Ioff ratio of approximately 106. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic RON. The current gain cut-off frequency (fT) and maximum stable gain cut-off frequency (fmax) were 5.2 GHz and 10.5 GHz, respectively, for the Al0.08GaN B.B. device.

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  • Creamer, Carlton

    BAE Systems Inc
    • 140 nm and 90 nm GaN MMIC Technology for Millimeter-wave Power Applications

      Jose Diaz, BAE Systems Inc
      David Brown, HRL Laboratories, LLC.
      Carlton Creamer, BAE Systems Inc
      Kanin Chu, BAE Systems Inc
      Richard Isaak, BAE Systems Inc
      Louis Mt. Pleasant, BAE Systems Inc
      Donald Mitchell, BAE Systems Inc
      Puneet Srivastava, BAE Systems Inc
      Wen Zhu, BAE Systems Inc
      Hong Lu, BAE Systems Inc

      This work describes an on-going effort to develop and mature a 140 nm GaN MMIC technology with a focus on efficient power amplification at frequencies ranging from DC to 50 GHz and a 90 nm technology targeted towards V- and W-band applications, and then release the technologies within a foundry process that is open to the DoD community.

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  • Crespo, Antonio

    Air Force Research Laboratory, Sensors Directorate
    • Dispersion Characteristics of ScAlN and ScAlGaN HEMTs by Pulsed I-V Measurements

      Kelson Chabak., Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Cathy Lee, Qorvo Inc.
      Yu Cao, Raytheon IDS Microelectronics, Novati Technologies, Inc. IQE
      Andy Xie, Qorvo
      Edward Beam, QORVO
      Antonio Crespo, Air Force Research Laboratory, Sensors Directorate
      Dennis Walker, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Robert Fitch, AFRL
      James Gillespie, Air Force Research Laboratory
      Andrew Green, Air Force Research Laboratory, Sensors Directorate

      We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

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  • Cunningham, Brian

    University of Illinois, Urbana-Champaign
    • Transfer of Thin Film Gallium Phosphide onto Glass for Integrable Optical Filters

      Maanav Ganjoo, University of Illinois, Urbana-Champaign
      John Carlson, University of Illinois, Urbana-Champaign
      Saoud Al-Mulla, University of Illinois, Urbana-Champaign
      James Brown, University of Illinois, Urbana-Champaign
      Brian Cunningham, University of Illinois, Urbana-Champaign
      John Dallesasse, University of Illinois at Urbana-Chamapign

      A single-layer optical filter made from thin film gallium phosphide (GaP) is envisioned and a fabrication flow is outlined, with current progress on process development reported. Ion-implantation is simulated and performed on bulk GaP with He+, followed by a field-assisted thermal bonding technique that simultaneously bonds a thin GaP film onto a borofloat glass substrate and removes the GaP substrate. The resulting thin films have consistent thickness, both within and between runs, and RMS surface roughness of < 10 nm. Dry-etch processes that further reduce the thin film material are characterized and designs for etching gratings into them are developed. This process is shown to be a reliable means of creating thin films of consistent thickness and smoothness in GaP, for the purpose of establishing visible wavelength filters for spectroscopic applications.

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  • D'Amico, John

    Semilab SDI
    • Micro-scale Imaging of Electrical Activity of Yield Killer Defects in 4H-SiC with Charge Assisted KFM and UV-Photoluminescence

      Jacek Lagowski, Semilab SDI, Tampa, FL,
      Marshall Wilson, Semilab SDI, Tampa, FL,
      David Greenock, X-Fab
      Dmitriy Marinskiy, Semilab SDI, Tampa, FL,
      Alexandre Savtchouk, Semilab SDI
      Anthony Ross III, Semilab SDI
      Carlos Almeida, Semilab SDI
      Bret Schrayer, Semilab SDI, Tampa, FL,
      John D’Amico, Semilab SDI

      In this work we compare non-contact charge-voltage imaging and UV-photoluminescence (UV-PL) imaging of yield killer defects in epitaxial 4H-SiC wafers.  Two significant findings are based on macro- and micro-scale imaging, respectively.  1- Whole wafer images demonstrate that only a fraction of the UV-PL defects in triangular, downfall and carrot categories are electrically active. 2- Micro-scale images reveal similarities and differences between PL and electrical defect images.  Presented for the first time, micrometer resolution leakage patterns within triangular defects are consistent with the microstructure modeling in reference 1. The results imply that the depletion layer leakage within killer defects corresponds to exposed 3C-SiC polytypes. This leakage may be a consequence of the lower 2.2eV energy gap of 3C-SiC compared to 3.3eV in 4H-SiC.

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  • D'Avanzo, Don

    Keysight Technologies, Inc.
    • A Study of Low-Annealing-Temperature Ohmic Contact on n-Type GaN Layers

      Shyh-Chiang Shen, Georgia Institute of Technology
      Minkyu Cho, Georgia Institute of Technology, Atlanta, GA
      Marzieh Bakhtiary Noodeh, Georgia Institute of Technology, Atlanta, GA
      Theeradetch Detchprohm, Georgia Institute of Technology
      Russell Dupuis, Georgia Tech
      Barry Wu, Keysight Technologies, Inc.
      Don D’Avanzo, Keysight Technologies, Inc.

      Typical n-type ohmic contact formation for GaN material systems requires high-temperature thermal processes. The high-temperature process often leads to a rough surface after the annealing step. Low-annealing-ohmic contact is advantageous to prevent undesired surface roughening on the metal stack during this thermal process.  We report an approach to achieve low contact resistance on n-type GaN layers using a nitrogen plasma and a conventional Ti/Al-based metal stacks.  We observed an as-deposit ohmic contact behavior on the n-type contact with a specific contact resistance (rc,sp) in the mid-E-6 Ω∙cm2 range.  The rc,sp was further reduced to  6.8E-7 Ω∙cm2 after an annealing step at 600 oC.

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  • Dalcanale, Stefano

    University of Bristol
    • Simulation of Leakage Induced Suppression of Bulk Dynamic RON in Power Switching GaN-on-Si HEMTs

      Martin Kuball, University of Bristol
      Michael Uren, University of Bristol
      Stefano Dalcanale, University of Bristol
      Feiyuan Yang, University of Bristol
      Ahmed Nejim, Silvaco Europe
      Stephen Wilson, Silvaco Europe

      Bulk induced dynamic RON in GaN-on-Si HEMTs is a serious performance limiting instability which remains a problem even in some commercially available power switching devices. Its origin is now reasonably well understood, however until now it has not been possible to simulate it using a realistic epitaxial stack. For the first time we successfully simulate the controlled suppression of bulk dynamic RON by adding a specific model for leakage along threading dislocations. This was undertaken using a commercially available standard TCAD simulator, allowing realistic device optimization in an advanced GaN HEMT design flow.

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  • Dallesasse, John

    University of Illinois at Urbana-Chamapign
    • Transfer of Thin Film Gallium Phosphide onto Glass for Integrable Optical Filters

      Maanav Ganjoo, University of Illinois, Urbana-Champaign
      John Carlson, University of Illinois, Urbana-Champaign
      Saoud Al-Mulla, University of Illinois, Urbana-Champaign
      James Brown, University of Illinois, Urbana-Champaign
      Brian Cunningham, University of Illinois, Urbana-Champaign
      John Dallesasse, University of Illinois at Urbana-Chamapign

      A single-layer optical filter made from thin film gallium phosphide (GaP) is envisioned and a fabrication flow is outlined, with current progress on process development reported. Ion-implantation is simulated and performed on bulk GaP with He+, followed by a field-assisted thermal bonding technique that simultaneously bonds a thin GaP film onto a borofloat glass substrate and removes the GaP substrate. The resulting thin films have consistent thickness, both within and between runs, and RMS surface roughness of < 10 nm. Dry-etch processes that further reduce the thin film material are characterized and designs for etching gratings into them are developed. This process is shown to be a reliable means of creating thin films of consistent thickness and smoothness in GaP, for the purpose of establishing visible wavelength filters for spectroscopic applications.

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  • Dallesasse, John

    University of Illinois at Urbana-Chamapign
    • Design and Fabrication Considerations for Transistor-Injected Quantum Cascade Lasers for Compact, Efficient, and Controllable Mid-Wave Infrared Lasing

      John Dallesasse, University of Illinois at Urbana-Chamapign
      Robert Kaufman, University of Illinois at Urbana-Champaign
      Patrick Su, University of Illinois at Urbana-Champaign
      Fu-Chen Hsiao, University of Illinois at Urbana-Champaign

      The transistor-injected quantum cascade laser (TI-QCL) is a novel design for a mid-wave infrared (MWIR) laser that seeks to overcome some of the primary limitations of standard quantum cascade lasers (QCLs). By growing the active cascade region within the base-collector junction of an n-p-n heterojunction bipolar transistor (HBT), independent control of the injection current and active region bias is achievable through the emitter current and base-collector reverse bias respectively. The active region bias is important to properly align the lasing states and to control the lasing wavelength. Physical design limitations of the TI-QCL and their effects on the fabrication process of samples is presented. In order to characterize device performance and validate fabrication improvements, InP-based device samples designed for λ = 7.3 µm emission are fabricated. Preliminary characterization results are shown in the form of diode measurements to validate the HBT electrical operation of the TI-QCL which is necessary to realize the optical benefits of the device.

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  • Das, Hrishikesh

    ON Semiconductor
    • Correlation study between molten KOH etching and laboratory X-ray Diffraction Imaging (X-ray topography) in n+ 4H-SiC wafers

      David Jacques, Bruker UK Ltd
      Vishal Shah, University of Warwick
      Richard Bytheway, Bruker UK Ltd
      Tamzin Lafford, Bruker UK Ltd
      Benjamin Renz, University of Warwick
      Peter Gammon, University of Warwick
      Paul Ryan, Bruker UK Ltd
      Hrishikesh Das, ON Semiconductor

      In order to meet the forecast growing demand of n+ SiC material, wafer suppliers will need to implement new metrology techniques to allow the detection of crystalline defects and ensure the quality of their materials. Incumbent techniques such as KOH etching have been used for many years but remain very costly as the wafers cannot be processed further. Alternative techniques such as X-ray Diffraction Imaging (X-ray Topography) can be used to detect crystalline defects non-destructively but studies have been limited to synchrotron radiation which cannot be used as an in-line characterization. In this paper, Bruker have used novel equipment (Sensus-CS) to study the correlation between laboratory X-ray Diffraction Imaging and KOH etching performed at the University of Warwick.

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  • Das, Hrishikesh

    ON Semiconductor USA
    • P-type and N-type Channeling Ion Implantation of SiC and Implications for Device Design and Fabrication

      Takashi Kuroi, Nissin Ion Equipment Inc.
      Hrishikesh Das, ON Semiconductor USA
      Swapna Sunkari, ON Semiconductor USA
      Joshua Justice, ON Semiconductor USA
      Roman Malousek, ON Semiconductor CZ
      Jan Chochol, ON Semiconductor CZ
      Ryota Wada, Nissin Ion Equipment Inc.

      This work focuses on evaluating and demonstrating channeled p-type and n-type implantations in silicon carbide in a repeatable mass-production environment. Range increase of about 3X is observed using channeled conditions as opposed to normal incident conditions for both Aluminum and Phosphorous. The various advantages enabled by this technology for advanced device designs are highlighted. Super-junction devices targeting the same voltage range can be fabricated using 1 or 2 lesser epitaxial regrowth layers.

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  • Day, Matthew

    SPTS Technologies Limited
    • Exploring the Challenges of Galiium Arsenide Plasma Dicing

      Owen Guy, Swansea University
      Will Worster, Swansea University
      Matthew Day, SPTS Technologies Limited
      M Jennings, KLA Corporation, SPTS Technologies Division, Swansea University
      Matt Elwin, Swansea University

      Plasma dicing of silicon wafers is beginning to move from pilot scale into mainstream production. Attention is now focusing on other market sectors which may benefit from a similar dicing approach.  The fragility of GaAs wafers leads to issues (such as wafer breakages, damage to die edges) during conventional wafer saw dicing. Although LASER techniques have been developed, they also have their own drawbacks – specifically sidewall quality.  A systematic investigation of the current capabilities of plasma dicing of GaAs substrates has been performed, developing technology which is both practical and economically viable. Preliminary results show smooth vertical sidewalls of trenches suitable for dicing thinned GaAs substrates at etch rates up to 23μm min-1.

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  • Decoutere, Stefaan

    Imec, Leuven, Belgium
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Deng, Ligang

    Oxford Instruments Plasma Technology
    • High Uniformity Etching of GaAs/AlGaAs VCSEL Mesa

      Ligang Deng, Oxford Instruments Plasma Technology
      Katie Hore, Oxford Instruments Plasma Technology
      Ning Zhang, Oxford Instruments Plasma Technology
      Stephanie Baclet, Oxford Instruments Plasma Technology

      The etching of uniform, repeatable GaAs/AlGaAs mesas is an important step in manufacturing VCSELs. This paper presents a high uniformity, low foot etching of mesa structures on 6” wafers. The improved uniformity permits the use of production-friendly optical endpoint techniques which can be used to stop on a specific layer in the VCSEL structure.

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  • Detchprohm, Theeradetch

    Georgia Institute of Technology
    • A Study of Low-Annealing-Temperature Ohmic Contact on n-Type GaN Layers

      Shyh-Chiang Shen, Georgia Institute of Technology
      Minkyu Cho, Georgia Institute of Technology, Atlanta, GA
      Marzieh Bakhtiary Noodeh, Georgia Institute of Technology, Atlanta, GA
      Theeradetch Detchprohm, Georgia Institute of Technology
      Russell Dupuis, Georgia Tech
      Barry Wu, Keysight Technologies, Inc.
      Don D’Avanzo, Keysight Technologies, Inc.

      Typical n-type ohmic contact formation for GaN material systems requires high-temperature thermal processes. The high-temperature process often leads to a rough surface after the annealing step. Low-annealing-ohmic contact is advantageous to prevent undesired surface roughening on the metal stack during this thermal process.  We report an approach to achieve low contact resistance on n-type GaN layers using a nitrogen plasma and a conventional Ti/Al-based metal stacks.  We observed an as-deposit ohmic contact behavior on the n-type contact with a specific contact resistance (rc,sp) in the mid-E-6 Ω∙cm2 range.  The rc,sp was further reduced to  6.8E-7 Ω∙cm2 after an annealing step at 600 oC.

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  • Dianat, Pouya

    Drexel University
    • Optoplasmonic Technology for High Performing Photodetectors

      Bahram Nabet, Drexel University
      Pouya Dianat, Drexel University
      Pouya Dianat, Nanograss Photonics
      Bahram Nabet, Nanograss Photonics

      We have developed a family of opto-plasmonic devices (OPDs) for next generation Tera-bits-per-second (Tbps) tele/data communication infrastructure. Particularly, a top illuminated optical detector is produced as an essential part of the value chain in PIC. This solves a bottleneck in high-speed PIC that currently use Germanium-based photodetectors. Specifically, a photodetector is demonstrated that operates at a 6x higher bandwidth and at 10-20x lower optical power conditions, compared to a commonly used 40-GHz pin device. These provide value for optics engineers to design: i) an optical receiver module with a %75 enhancement in reliability, and ii) an optical link with 10x extension in length.

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  • Dianat, Pouya

    Nanograss Photonics
    • Optoplasmonic Technology for High Performing Photodetectors

      Bahram Nabet, Drexel University
      Pouya Dianat, Drexel University
      Pouya Dianat, Nanograss Photonics
      Bahram Nabet, Nanograss Photonics

      We have developed a family of opto-plasmonic devices (OPDs) for next generation Tera-bits-per-second (Tbps) tele/data communication infrastructure. Particularly, a top illuminated optical detector is produced as an essential part of the value chain in PIC. This solves a bottleneck in high-speed PIC that currently use Germanium-based photodetectors. Specifically, a photodetector is demonstrated that operates at a 6x higher bandwidth and at 10-20x lower optical power conditions, compared to a commonly used 40-GHz pin device. These provide value for optics engineers to design: i) an optical receiver module with a %75 enhancement in reliability, and ii) an optical link with 10x extension in length.

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  • Diaz, Jose

    BAE Systems Inc
    • 140 nm and 90 nm GaN MMIC Technology for Millimeter-wave Power Applications

      Jose Diaz, BAE Systems Inc
      David Brown, HRL Laboratories, LLC.
      Carlton Creamer, BAE Systems Inc
      Kanin Chu, BAE Systems Inc
      Richard Isaak, BAE Systems Inc
      Louis Mt. Pleasant, BAE Systems Inc
      Donald Mitchell, BAE Systems Inc
      Puneet Srivastava, BAE Systems Inc
      Wen Zhu, BAE Systems Inc
      Hong Lu, BAE Systems Inc

      This work describes an on-going effort to develop and mature a 140 nm GaN MMIC technology with a focus on efficient power amplification at frequencies ranging from DC to 50 GHz and a 90 nm technology targeted towards V- and W-band applications, and then release the technologies within a foundry process that is open to the DoD community.

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  • Dlugolecka, Aleksandra

    United Monolithic Semiconductors GmbH, Ulm
    • Impact of water content in NMP on ohmic contacts in GaN HEMT technologies

      Michael Hosch, United Monolithic Semiconductors
      Alexander Hugger, United Monolithic Semiconductors GmbH, Ulm
      Aleksandra Dlugolecka, United Monolithic Semiconductors GmbH, Ulm
      Hermann Stieglauer, United Monolithic Semiconductors Germany
      Raphael Ehrbrecht, United Monolithic Semiconductors GmbH, Ulm

      Wet chemical lift off in N-Methyl-2-pyrrolidone (NMP) is widely used in GaN HEMT Front End manufacturing.  In case of a Ti-Al-Ni-Au based metal stack for ohmic contacts, the quality of the lift-off process is much depending on the water content in the solvent NMP. In this paper, it will be shown that the metal stack can be attacked during lift off in NMP with too high water content. Additionally, environmental impacts on the hygroscopy of NMP are investigated in order to keep moisture below a certain level and avoid optical defects on ohmic contacts after lift off.

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  • DOGMUS, Ezgi

    Yole Développement
    • Market opportunities for Wide-Band gap semiconductors in EV/HEV applications

      Ahmed Ben-Slimane, Yole Développement 75 cours Emile Zola, 69100 Villeurbanne France
      Hong LIN, Yole Développement 75 cours Emile Zola, 69100 Villeurbanne France
      Ezgi DOGMUS, Yole Développement

      The high growth of the EV/HEV market impacted significantly the wide bandgap semiconductor industry, creating new opportunities and a competition between SiC and GaN in many applications such as on-board chargers, DC-DC converters and main inverters. This paper provides an overview of SiC and GaN device technology, including Yole Développement’s understanding of the market’s current dynamics and future evolution of wide band gap materials compared to mainstream Silicon power electronics market.

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    • Impact of high volume 3D Sensing applications on Compound Semiconductor Industry

      Pierrick Boulay, Yole Developpement
      Hong LIN, Yole Developpement
      Ahmed Ben-Slimane, Yole Developpement
      Pars Mukish, Yole Developpement
      Ezgi DOGMUS, Yole Développement
    • 5G impact on Wireless Infrastructure and Compound Semiconductor Industry

      Ahmed Ben-Slimane, Yole Developpement
      Antoine Bonnabel, Yole Developpement
      Cédric MALAQUIN, Yole Developpement
      Claire Troadec, Yole Developpement
      Hong LIN, Yole Developpement
      Ezgi DOGMUS, Yole Développement

      The paper presents the market overview of different compound semiconductor such as GaN, GaAs, and InP impacted by the deployment of 5G in wireless infrastructure. The value chain from wafer and epitaxy to device level is covered, as well as technology and market trends and Yole’s forecast for the coming years.

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  • Doonan, Sean

    Skyworks Solutions, Inc.
    • The Effect of Delay Between Pre-clean and Metal Deposition on the Forward Current Voltage Characteristics of Schottky Devices

      Eric Finchem, MACOM
      Debdas Pal, MACOM
      Lorain Ross, Skyworks Solutions, Inc.
      Sean Doonan, Skyworks Solutions, Inc.
      Edmund Burke, Skyworks Solutions, Inc.

      Schottky devices play an important role in modern electronics. The forward biased current-voltage characteristics of such devices are linear on a semi-logarithm scale at intermediate bias voltages. However, the curve deviates from linearity at higher voltage primarily due to series resistance. The applied forward voltage on the device is equal to the sum of the voltage drops across the (1) junction, (2) series resistance, (3) depletion layer and (4) any parasitic resistive layer between the Schottky metal and the semiconductor. Therefore, the interface between the metal and the semiconductor plays an important role in determining the critical parameters of Schottky devices. In this investigation a controlled delay was introduced between the pre-metal clean and Schottky metal deposition steps of the fabrication process to study the effects of naturally grown oxide on the forward characteristics of the Schottky devices.  The results of the investigation indicate such delays cause significant increases in series resistance and ideality factor, as well as a decrease in barrier height.

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  • Dorsey, Donald

    Air Force Research Laboratory Materials and Manufacturing Directorate
    • Self-Aligned Refractory Metal Gate Scaling in β-Ga2O3 MOSFETs

      Kelson Chabak, Air Force Research Laboratory, Sensors Directorate
      Kyle Liddy, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Andrew Green, Air Force Research Laboratory, Sensors Directorate
      Thaddeus Asel, Air Force Research Laboratory, Wright Patterson AFB, OH, USA
      Shin Mou, Air Force Research Laboratory, Wright Patterson AFB, OH
      Kevin Leedy, Air Force Research Laboratory, Sensors Directorate
      Donald Dorsey, Air Force Research Laboratory Materials and Manufacturing Directorate

      This work characterizes the effects of gate-length (LG) scaling in a self-aligned gate (SAG) β-Ga2O3 MOSFET process. Additional performance gains are expected by extending the SAG process from large LG to sub-micrometer dimensions.  This data incorporates LG scaling down to 200 nm to improve device performance in Ga2O3 SAG MOSFETs using a stepper lithography process to define sub-micron gate lengths.

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  • Drechsler, Annaliese

    Northrop Grumman (MS), Linthicum, MD
    • 100nm, Three-dimensional T-Gate for SLCFET Amplifiers

      Robert Howell, Northrop Grumman Corporation
      Annaliese Drechsler, Northrop Grumman (MS), Linthicum, MD
      Ken Nagamatsu, Northrop Grumman Corporation
      Kevin Frey, Northrop Grumman Corporation
      Monique Farrell, Northrop Grumman Corporation
      Georges Siddiqi, HRL Laboratories
      M. Scimonelli, Northrop Grumman (MS), Linthicum, MD
      Jordan Merkle, Northrop Grumman Corporation
      Josephine Chang, Northrop Grumman Corporation

      This report describes the first demonstration of a 100nm T-gate for the Superlattice Castellation Field Effect Transistor (SLCFET) amplifier. The SLCFET amplifier device utilizes a superlattice of GaN/AlGaN channels, which enables a high charge density and low source resistance. A three-dimensional T-gate structure provides electrostatic control of the channels while maintaining high gain. Improvements to the T-gate process have allowed for the scaling of the gate down to 100nm while maintaining excellent gate control, with an on to off current ratio exceeding 107. This gate scaling allows the device to reach FT / FMAX of 70/110 GHz with full passivation to maintain compatibility with the productionized SLCFET switch process.

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  • Dubagunta, Venu

    MAX International Engineering Group
    • Cost Reduction Opportunities in CS Maintenance & Inventory Management

      Dimitry Gurevich, MAX I.E.G. LLC
      ILIA KAPLAN, The MAX Group
      Venu Dubagunta, MAX International Engineering Group

      Major cost gaps were identified from a benchmark (BM) study for a Semiconductor fab. The study triggered deep-dive assessments of both maintenance practices and supply chain business processes. Those assessments uncovered significant improvement opportunities. In this paper, we discuss the approach used to identify and quantify those opportunities, and share important results and observations with the Compound Semiconductor (CS) manufacturing community.

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  • Dupuis, Russell

    Georgia Tech
    • A Study of Low-Annealing-Temperature Ohmic Contact on n-Type GaN Layers

      Shyh-Chiang Shen, Georgia Institute of Technology
      Minkyu Cho, Georgia Institute of Technology, Atlanta, GA
      Marzieh Bakhtiary Noodeh, Georgia Institute of Technology, Atlanta, GA
      Theeradetch Detchprohm, Georgia Institute of Technology
      Russell Dupuis, Georgia Tech
      Barry Wu, Keysight Technologies, Inc.
      Don D’Avanzo, Keysight Technologies, Inc.

      Typical n-type ohmic contact formation for GaN material systems requires high-temperature thermal processes. The high-temperature process often leads to a rough surface after the annealing step. Low-annealing-ohmic contact is advantageous to prevent undesired surface roughening on the metal stack during this thermal process.  We report an approach to achieve low contact resistance on n-type GaN layers using a nitrogen plasma and a conventional Ti/Al-based metal stacks.  We observed an as-deposit ohmic contact behavior on the n-type contact with a specific contact resistance (rc,sp) in the mid-E-6 Ω∙cm2 range.  The rc,sp was further reduced to  6.8E-7 Ω∙cm2 after an annealing step at 600 oC.

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  • Ebrish, Mona

    Vanderbilt University, Nashville, TN
    • Exploring the capability of Hyperspectral Electroluminescence for process monitoring in vertical GaN devices

      Karl D. Hobart, U.S. Naval Research Laboratory
      Mona Ebrish, Vanderbilt University, Nashville, TN
      Travis J. Anderson, U.S. Naval Research Laboratory
      James Gallagher, U.S. Naval Research Laboratory
      Joseph Spencer, U.S. Naval Research Laboratory, Washington, DC, USA, Virginia Tech
      Jennifer Hite, U.S. Naval Research Laboratory
      Michael Mastro, U.S. Naval Research Laboratory

      GaN is a promising material for more efficient high frequency and high voltage power switching. However, GaN still is not the common material for power electronics due to immature substrate, homoepitaxial growth, and processing technology. Electroluminescence is a promising method to predict failure points due to high field stress, which can assist in the separation of inherent defects stemming from substrate quality, and from process-induced defects as well as identify problems related to proper edge termination design. In this work, we compare the Electroluminescence signatures of devices on inhomogeneous substrates to DC I-V behavior to demonstrate the utility of the technique for process monitoring.

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  • Ebrish, Mona

    NRC Postdoc Fellow Residing at the U.S. Naval Research Laboratory
    • Predicting Vertical GaN Diode Quality using Long Range Optical tests on Substrates

      Francis Kub, U.S. Naval Research Laboratory
      James Gallagher, U.S. Naval Research Laboratory
      Andrew Koehler, Naval Research Laboratory
      Mona Ebrish, NRC Postdoc Fellow Residing at the U.S. Naval Research Laboratory
      Michael Mastro, U.S. Naval Research Laboratory
      Jennifer Hite, U.S. Naval Research Laboratory
      Karl Holbart, U.S. Naval Research Laboratory

      It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

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  • Edo, Masaharu

    Fuji Electric Co., Ltd.
    • Recent development of vertical GaN planar MOSFETs fabricated by Ion Implantation

      Masaharu Edo, Fuji Electric Co., Ltd.
      Ryo Tanaka, Fuji Electric Co., Ltd.
      Shinya Takashima, Fuji Electric Co., Ltd.
      Katsunori Ueno, Fuji Electric Co., Ltd.
      Hideaki Matsuyama, Fuji Electric Co., Ltd.
      Yuta Fukushima, Fuji Electric Co., Ltd.

      We have demonstrated the vertical GaN planar-gate MOSFETs fabricated by an ion implantation process.  The fabricated GaN vertical MOSFET shows a specific on-resistance of 2.78 mΩ cm2 and a breakdown voltage of 1200 V, by applying a Mg and N sequential implantation to improve the breakdown voltage of the pn-junction and the control of the MOS channel characteristics on the p-type ion implanted layer.  Consequently, the vertical GaN planar-gate MOSFETs with high breakdown voltage and low on-resistance could be realized by ion implantation process.  On the other hand, there are still many challenges for realizing practical GaN vertical MOSFETs, so continuous development is necessary.

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  • Ehrbrecht, Raphael

    United Monolithic Semiconductors GmbH, Ulm
    • Impact of water content in NMP on ohmic contacts in GaN HEMT technologies

      Michael Hosch, United Monolithic Semiconductors
      Alexander Hugger, United Monolithic Semiconductors GmbH, Ulm
      Aleksandra Dlugolecka, United Monolithic Semiconductors GmbH, Ulm
      Hermann Stieglauer, United Monolithic Semiconductors Germany
      Raphael Ehrbrecht, United Monolithic Semiconductors GmbH, Ulm

      Wet chemical lift off in N-Methyl-2-pyrrolidone (NMP) is widely used in GaN HEMT Front End manufacturing.  In case of a Ti-Al-Ni-Au based metal stack for ohmic contacts, the quality of the lift-off process is much depending on the water content in the solvent NMP. In this paper, it will be shown that the metal stack can be attacked during lift off in NMP with too high water content. Additionally, environmental impacts on the hygroscopy of NMP are investigated in order to keep moisture below a certain level and avoid optical defects on ohmic contacts after lift off.

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  • Elkan, Edward

    Qorvo Inc.
    • eDataLyzer Application on Solving DS Yield Issue with Starburst Pattern

      Kim Kok Gan, Bistel America Inc
      Yiping Wang, Qorvo Inc.
      Robert Waco, Qorvo Inc.
      Matthew Johnson, Qorvo Inc.
      Pat Hamilton, Qorvo Inc.
      Jinhong Yang, Qorvo
      Dana Schwartz
      Corey Nevers, Qorvo, Inc
      Edward Elkan, Qorvo Inc.
      Kaushik Vaidyanathan, Qorvo Inc.

      A die sort (DS) yield loss forming a ‘starburst’ pattern in a wafermap was observed in a pHEMT technology manufactured by Qorvo. Typical data analysis performed by yield engineers was unable to correlate the failure root cause to a specific process step. To help drive to root cause, Bistel was consulted on the use of eDataLyzer (eDL) software.

      This paper will describe the ‘starburst’ DS yield loss pattern in details, followed by the application of Bistel’s eDL software combined with process tool Fault Detection and Correlation (FDC), and end with the validation of the failure mode.

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  • Elliot, Lisza

    MACOM
    • Thermal Stability, Uniformity and Electrical Properties of Sputtered and Evaporated NiCr Thin Film Resistors

      Peter Ersland, Macom Technology Solutions
      Pradeep Waduge, Macom Technology Solutions
      Maik Katko, Macom Technology Solutions
      Lisza Elliot, MACOM

      NiCr is one of the most commonly used resistive materials for fabricating precision thin film resistors due to its wide range of resistivity, low temperature coefficient of resistivity (TCR), and high stability of electrical properties. NiCr thin film resistors are usually manufactured by evaporation or sputtering. It is well known that thermal evaporation of NiCr from a finite mass of molten alloy causes a film composition change away from the composition of the source, as well as film composition changes from run to run. Some electrical properties of NiCr thin film resistors strongly depend on the film microstructure (i.e. Ni:Cr ratio) in addition to its spatial geometry (film thickness) and the deposition parameters in the evaporator. As a result, while film thickness and deposition parameters are well controlled, often time resistivity of evaporated NiCr thin film resistors goes out of spec. Therefore, in this paper we are investigating the possibility of replacing the evaporated NiCr thin films with the sputtered NiCr thin films as resistors. Here, we present a comprehensive study of NiCr thin film resistors developed using DC sputtering system and discuss the effects of sputtering process parameters and substrate conditions on film microstructure, TCR and electrical properties.

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  • Elwin, Matt

    Swansea University
    • Exploring the Challenges of Galiium Arsenide Plasma Dicing

      Owen Guy, Swansea University
      Will Worster, Swansea University
      Matthew Day, SPTS Technologies Limited
      M Jennings, KLA Corporation, SPTS Technologies Division, Swansea University
      Matt Elwin, Swansea University

      Plasma dicing of silicon wafers is beginning to move from pilot scale into mainstream production. Attention is now focusing on other market sectors which may benefit from a similar dicing approach.  The fragility of GaAs wafers leads to issues (such as wafer breakages, damage to die edges) during conventional wafer saw dicing. Although LASER techniques have been developed, they also have their own drawbacks – specifically sidewall quality.  A systematic investigation of the current capabilities of plasma dicing of GaAs substrates has been performed, developing technology which is both practical and economically viable. Preliminary results show smooth vertical sidewalls of trenches suitable for dicing thinned GaAs substrates at etch rates up to 23μm min-1.

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  • Ersland, Peter

    Macom Technology Solutions
    • Thermal Stability, Uniformity and Electrical Properties of Sputtered and Evaporated NiCr Thin Film Resistors

      Peter Ersland, Macom Technology Solutions
      Pradeep Waduge, Macom Technology Solutions
      Maik Katko, Macom Technology Solutions
      Lisza Elliot, MACOM

      NiCr is one of the most commonly used resistive materials for fabricating precision thin film resistors due to its wide range of resistivity, low temperature coefficient of resistivity (TCR), and high stability of electrical properties. NiCr thin film resistors are usually manufactured by evaporation or sputtering. It is well known that thermal evaporation of NiCr from a finite mass of molten alloy causes a film composition change away from the composition of the source, as well as film composition changes from run to run. Some electrical properties of NiCr thin film resistors strongly depend on the film microstructure (i.e. Ni:Cr ratio) in addition to its spatial geometry (film thickness) and the deposition parameters in the evaporator. As a result, while film thickness and deposition parameters are well controlled, often time resistivity of evaporated NiCr thin film resistors goes out of spec. Therefore, in this paper we are investigating the possibility of replacing the evaporated NiCr thin films with the sputtered NiCr thin films as resistors. Here, we present a comprehensive study of NiCr thin film resistors developed using DC sputtering system and discuss the effects of sputtering process parameters and substrate conditions on film microstructure, TCR and electrical properties.

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  • Fahle, Dirk

    AIXTRON SE
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Faili, Firooz

    Element Six Technologies, Santa Clara, CA
    • GaN-on-diamond: the correlation between interfacial toughness and thermal resistance

      Daniel Francis, Akash Systems, San Francisco, CA, USA
      Daniel Field, University of Bristol
      Caho Yuan, University of Bristol
      Roland Simon, Thermap Solutions
      Daniel Twitchen, Element Six Technologies
      Firooz Faili, Element Six Technologies, Santa Clara, CA
      Dong Liu, University of Oxford, University of Bristol
      Matin Kuball, University of Bristol, Bristol, UK,

      A nanoindentation induced blistering method has been used to extract the GaN/diamond interfacial toughness (adhesion energy) from four types of GaN-on-diamond samples with varying SiNx interlayer thicknesses. The mode I energy release rate (GIC) was quantified and is presented. Additionally, transient thermoreflectance has been used to measure the thermal boundary resistance (TBR) between the GaN and the diamond substrate. It was found that a thin SiNx interlayer resulted in a lower TBR (15 m2 K GW-1) whilst maintaining a reasonable interfacial toughness (1.4±0.5 J m-2). For interlayers of a similar thickness, samples with a high interfacial toughness and high residual stresses in the GaN had a smaller TBR. This indicates that the intrinsic interfacial characteristics that enhanced the interfacial toughness could be beneficial in improving the TBR.

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  • Farrell, Monique

    Northrop Grumman Corporation
    • 100nm, Three-dimensional T-Gate for SLCFET Amplifiers

      Robert Howell, Northrop Grumman Corporation
      Annaliese Drechsler, Northrop Grumman (MS), Linthicum, MD
      Ken Nagamatsu, Northrop Grumman Corporation
      Kevin Frey, Northrop Grumman Corporation
      Monique Farrell, Northrop Grumman Corporation
      Georges Siddiqi, HRL Laboratories
      M. Scimonelli, Northrop Grumman (MS), Linthicum, MD
      Jordan Merkle, Northrop Grumman Corporation
      Josephine Chang, Northrop Grumman Corporation

      This report describes the first demonstration of a 100nm T-gate for the Superlattice Castellation Field Effect Transistor (SLCFET) amplifier. The SLCFET amplifier device utilizes a superlattice of GaN/AlGaN channels, which enables a high charge density and low source resistance. A three-dimensional T-gate structure provides electrostatic control of the channels while maintaining high gain. Improvements to the T-gate process have allowed for the scaling of the gate down to 100nm while maintaining excellent gate control, with an on to off current ratio exceeding 107. This gate scaling allows the device to reach FT / FMAX of 70/110 GHz with full passivation to maintain compatibility with the productionized SLCFET switch process.

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  • Fay, Patrick

    University of Notre Dame
    • RF Harmonic Distortion of Coplanar Waveguides on GaN-on-Si and GaN-on-SiC Substrates

      Patrick Fay, University of Notre Dame
      Lina Cao, Keysight Technologies
      Hansheng Ye, University of Notre Dame
      Jingshan Wang, Notre Dame
      Hugues Marchand, IQE
      Wayne Johnson, IQE

      The RF harmonic distortion of coplanar waveguides (CPWs) fabricated on AlGaN/GaN HEMT heterostructures grown on both high-resistivity Si (GaN-on-Si) and semi-insulating SiC (GaN-on-SiC) substrates is reported for the first time. The loss performance and the nonlinear behavior of the CPW lines were experimentally characterized using both small- and large-signal measurements. From 100 MHz to 20 GHz, low loss (less than 0.3 dB/mm at 20 GHz) was achieved; the attenuation of CPW lines on the GaN-on-Si substrate is ~0.05 dB/mm higher than that of the GaN-on-SiC substrate. The harmonic distortion levels of the GaN-on-Si substrate and GaN-on-SiC were also evaluated experimentally; in contrast to the small-signal loss, more significant differences in second- and third-order nonlinearity, and thus intermodulation, are observed between Si and SiC substrates. Large-signal characterization of the GaN-on-Si substrate was carried out over temperature from 25 °C to 175 °C.  Due to increases in substrate conductivity with temperature, the harmonic distortion levels are found to increase significantly at temperatures above 75 °C.

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  • Feng, Milton

    University of Illinois, Urbana-Champaign
    • 850 nm GaAs P-i-N Photodiodes for 50 Gb/s Optical Links with Dark Current below 1 pA

      Dufei Wu, University of Illinois at Urbana Champaign
      Yu-Ting Peng, University of Illinois, Urbana-Champaign
      Milton Feng, University of Illinois, Urbana-Champaign

      Fabrication techniques and experimental data are presented for 850 nm GaAs P-i-N photodiodes designed for 50 Gb/s optical links. Optimizations in the device structure and the selective dry etching process reduce dark current below 1pA. Responsivity is shown to be comparable to commercial devices with similar dimensions. And microwave measurement shows a highest bandwidth of above 30 GHz, indicating potential for 60 Gb/s operation. Data rate testing is performed with a VCSEL up to 50 Gb/s, showing clear eye diagrams.

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  • Feng, Milton

    University of Illinois Urbana-Champaign
    • Wet-etching Process Problem Identification in Type-II InP DHBT for 5G Power Application

      Milton Feng, University of Illinois Urbana-Champaign
      Yu-Ting Peng, University of Illinois at Urbana Champaign
      Xin Yu, University of Illinois at Urbana-Champaign

      Wet-etching issues in type-II DHBT process fabricated by standard triple-mesa wet-etching have been identified and reported in this paper. For comparison, devices fabricated by hybrid-etching with incorporation of inductively-coupled-plasma (ICP) are also present. With better uniformity and yield, hybrid-etching process can potentially lead to a more reliable and reproducible process for 5G power amplifier application.

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  • Feygelson, Tatyana

    Naval Research Laboratory
    • Formation of Diamond Superjunctions to Enable GaN-Based Super-Lattice Power Amplifiers with Diamond Enhanced Superjunctions (SPADES)

      Geoffrey Foster, Jacobs Inc., Washington DC
      Tatyana Feygelson, Naval Research Laboratory
      James Gallagher, ASEE Postdoctoral Fellow Residing at NRL
      Josephine Chang, Northrop Grumman
      Shamima Afroz, Northrop Grumman
      Ken Nagamatsu, Northrop Grumman
      Robert Howell, Northrop Grumman
      Fritz Kub, Naval Research Laboratory

      The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

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  • Field, Daniel

    University of Bristol
    • GaN-on-diamond: the correlation between interfacial toughness and thermal resistance

      Daniel Francis, Akash Systems, San Francisco, CA, USA
      Daniel Field, University of Bristol
      Caho Yuan, University of Bristol
      Roland Simon, Thermap Solutions
      Daniel Twitchen, Element Six Technologies
      Firooz Faili, Element Six Technologies, Santa Clara, CA
      Dong Liu, University of Oxford, University of Bristol
      Matin Kuball, University of Bristol, Bristol, UK,

      A nanoindentation induced blistering method has been used to extract the GaN/diamond interfacial toughness (adhesion energy) from four types of GaN-on-diamond samples with varying SiNx interlayer thicknesses. The mode I energy release rate (GIC) was quantified and is presented. Additionally, transient thermoreflectance has been used to measure the thermal boundary resistance (TBR) between the GaN and the diamond substrate. It was found that a thin SiNx interlayer resulted in a lower TBR (15 m2 K GW-1) whilst maintaining a reasonable interfacial toughness (1.4±0.5 J m-2). For interlayers of a similar thickness, samples with a high interfacial toughness and high residual stresses in the GaN had a smaller TBR. This indicates that the intrinsic interfacial characteristics that enhanced the interfacial toughness could be beneficial in improving the TBR.

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  • Finchem, Eric

    MACOM
    • The Effect of Delay Between Pre-clean and Metal Deposition on the Forward Current Voltage Characteristics of Schottky Devices

      Eric Finchem, MACOM
      Debdas Pal, MACOM
      Lorain Ross, Skyworks Solutions, Inc.
      Sean Doonan, Skyworks Solutions, Inc.
      Edmund Burke, Skyworks Solutions, Inc.

      Schottky devices play an important role in modern electronics. The forward biased current-voltage characteristics of such devices are linear on a semi-logarithm scale at intermediate bias voltages. However, the curve deviates from linearity at higher voltage primarily due to series resistance. The applied forward voltage on the device is equal to the sum of the voltage drops across the (1) junction, (2) series resistance, (3) depletion layer and (4) any parasitic resistive layer between the Schottky metal and the semiconductor. Therefore, the interface between the metal and the semiconductor plays an important role in determining the critical parameters of Schottky devices. In this investigation a controlled delay was introduced between the pre-metal clean and Schottky metal deposition steps of the fabrication process to study the effects of naturally grown oxide on the forward characteristics of the Schottky devices.  The results of the investigation indicate such delays cause significant increases in series resistance and ideality factor, as well as a decrease in barrier height.

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  • Fitch, Robert

    AFRL
    • Dispersion Characteristics of ScAlN and ScAlGaN HEMTs by Pulsed I-V Measurements

      Kelson Chabak., Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Cathy Lee, Qorvo Inc.
      Yu Cao, Raytheon IDS Microelectronics, Novati Technologies, Inc. IQE
      Andy Xie, Qorvo
      Edward Beam, QORVO
      Antonio Crespo, Air Force Research Laboratory, Sensors Directorate
      Dennis Walker, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Robert Fitch, AFRL
      James Gillespie, Air Force Research Laboratory
      Andrew Green, Air Force Research Laboratory, Sensors Directorate

      We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

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  • Foster, Geoffrey

    Jacobs Inc., Washington DC
    • Formation of Diamond Superjunctions to Enable GaN-Based Super-Lattice Power Amplifiers with Diamond Enhanced Superjunctions (SPADES)

      Geoffrey Foster, Jacobs Inc., Washington DC
      Tatyana Feygelson, Naval Research Laboratory
      James Gallagher, ASEE Postdoctoral Fellow Residing at NRL
      Josephine Chang, Northrop Grumman
      Shamima Afroz, Northrop Grumman
      Ken Nagamatsu, Northrop Grumman
      Robert Howell, Northrop Grumman
      Fritz Kub, Naval Research Laboratory

      The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

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  • Francis, Daniel

    Akash Systems, San Francisco, CA, USA
    • GaN-on-diamond: the correlation between interfacial toughness and thermal resistance

      Daniel Francis, Akash Systems, San Francisco, CA, USA
      Daniel Field, University of Bristol
      Caho Yuan, University of Bristol
      Roland Simon, Thermap Solutions
      Daniel Twitchen, Element Six Technologies
      Firooz Faili, Element Six Technologies, Santa Clara, CA
      Dong Liu, University of Oxford, University of Bristol
      Matin Kuball, University of Bristol, Bristol, UK,

      A nanoindentation induced blistering method has been used to extract the GaN/diamond interfacial toughness (adhesion energy) from four types of GaN-on-diamond samples with varying SiNx interlayer thicknesses. The mode I energy release rate (GIC) was quantified and is presented. Additionally, transient thermoreflectance has been used to measure the thermal boundary resistance (TBR) between the GaN and the diamond substrate. It was found that a thin SiNx interlayer resulted in a lower TBR (15 m2 K GW-1) whilst maintaining a reasonable interfacial toughness (1.4±0.5 J m-2). For interlayers of a similar thickness, samples with a high interfacial toughness and high residual stresses in the GaN had a smaller TBR. This indicates that the intrinsic interfacial characteristics that enhanced the interfacial toughness could be beneficial in improving the TBR.

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  • Frey, Kevin

    Northrop Grumman Corporation
    • 100nm, Three-dimensional T-Gate for SLCFET Amplifiers

      Robert Howell, Northrop Grumman Corporation
      Annaliese Drechsler, Northrop Grumman (MS), Linthicum, MD
      Ken Nagamatsu, Northrop Grumman Corporation
      Kevin Frey, Northrop Grumman Corporation
      Monique Farrell, Northrop Grumman Corporation
      Georges Siddiqi, HRL Laboratories
      M. Scimonelli, Northrop Grumman (MS), Linthicum, MD
      Jordan Merkle, Northrop Grumman Corporation
      Josephine Chang, Northrop Grumman Corporation

      This report describes the first demonstration of a 100nm T-gate for the Superlattice Castellation Field Effect Transistor (SLCFET) amplifier. The SLCFET amplifier device utilizes a superlattice of GaN/AlGaN channels, which enables a high charge density and low source resistance. A three-dimensional T-gate structure provides electrostatic control of the channels while maintaining high gain. Improvements to the T-gate process have allowed for the scaling of the gate down to 100nm while maintaining excellent gate control, with an on to off current ratio exceeding 107. This gate scaling allows the device to reach FT / FMAX of 70/110 GHz with full passivation to maintain compatibility with the productionized SLCFET switch process.

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  • Fukuhara, Noboru

    SCIOCS Company Ltd.
    • Fabrication of Recessed Structures for GaN HEMTs by a Simple Wet Etching Process

      Taketomo Sato, Hokkaido University
      Fumimasa Horikiri, Sciocs Company Limited
      Noboru Fukuhara, SCIOCS Company Ltd.
      Masachika Toguchi, Hokkaido University
      Kazuki Miwa, Hokkaido University
      Yoshinobu Narita, Sciocs Company Limited
      Osamu Ichikawa, SCIOCS Company Ltd.
      Ryota Isono, SCIOCS Company Ltd.
      Takeshi Tanaka, SCIOCS Company Ltd.

      Photoelectrochemical (PEC) etching is a promising technology for fabricating GaN devices with low damage. In the simple contactless PEC (CL–PEC) etching process that includes K2S2O8 in the electrolyte as an oxidizing agent, a sample is dipped into the electrolyte under UV irradiation. In this study, we applied CL–PEC to the gate-recess process of GaN HEMTs on an SiC substrate. The etching depth of the recess showed considerable reproducibility by the self-termination feature, and the residual AlGaN layer thickness was approximately 5 nm. The Schottky gate HEMTs with a recessed structure showed the normally off characteristics, and the Vth value was +0.4 V with a standard deviation of ±3.8 mV.

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  • Fukushima, Yuta

    Fuji Electric Co., Ltd.
    • Recent development of vertical GaN planar MOSFETs fabricated by Ion Implantation

      Masaharu Edo, Fuji Electric Co., Ltd.
      Ryo Tanaka, Fuji Electric Co., Ltd.
      Shinya Takashima, Fuji Electric Co., Ltd.
      Katsunori Ueno, Fuji Electric Co., Ltd.
      Hideaki Matsuyama, Fuji Electric Co., Ltd.
      Yuta Fukushima, Fuji Electric Co., Ltd.

      We have demonstrated the vertical GaN planar-gate MOSFETs fabricated by an ion implantation process.  The fabricated GaN vertical MOSFET shows a specific on-resistance of 2.78 mΩ cm2 and a breakdown voltage of 1200 V, by applying a Mg and N sequential implantation to improve the breakdown voltage of the pn-junction and the control of the MOS channel characteristics on the p-type ion implanted layer.  Consequently, the vertical GaN planar-gate MOSFETs with high breakdown voltage and low on-resistance could be realized by ion implantation process.  On the other hand, there are still many challenges for realizing practical GaN vertical MOSFETs, so continuous development is necessary.

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  • Gallagher, James

    U.S. Naval Research Laboratory
    • Exploring the capability of Hyperspectral Electroluminescence for process monitoring in vertical GaN devices

      Karl D. Hobart, U.S. Naval Research Laboratory
      Mona Ebrish, Vanderbilt University, Nashville, TN
      Travis J. Anderson, U.S. Naval Research Laboratory
      James Gallagher, U.S. Naval Research Laboratory
      Joseph Spencer, U.S. Naval Research Laboratory, Washington, DC, USA, Virginia Tech
      Jennifer Hite, U.S. Naval Research Laboratory
      Michael Mastro, U.S. Naval Research Laboratory

      GaN is a promising material for more efficient high frequency and high voltage power switching. However, GaN still is not the common material for power electronics due to immature substrate, homoepitaxial growth, and processing technology. Electroluminescence is a promising method to predict failure points due to high field stress, which can assist in the separation of inherent defects stemming from substrate quality, and from process-induced defects as well as identify problems related to proper edge termination design. In this work, we compare the Electroluminescence signatures of devices on inhomogeneous substrates to DC I-V behavior to demonstrate the utility of the technique for process monitoring.

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  • Gallagher, James

    ASEE Postdoctoral Fellow Residing at NRL
    • Formation of Diamond Superjunctions to Enable GaN-Based Super-Lattice Power Amplifiers with Diamond Enhanced Superjunctions (SPADES)

      Geoffrey Foster, Jacobs Inc., Washington DC
      Tatyana Feygelson, Naval Research Laboratory
      James Gallagher, ASEE Postdoctoral Fellow Residing at NRL
      Josephine Chang, Northrop Grumman
      Shamima Afroz, Northrop Grumman
      Ken Nagamatsu, Northrop Grumman
      Robert Howell, Northrop Grumman
      Fritz Kub, Naval Research Laboratory

      The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

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  • Gallagher, James

    U.S. Naval Research Laboratory
    • Predicting Vertical GaN Diode Quality using Long Range Optical tests on Substrates

      Francis Kub, U.S. Naval Research Laboratory
      James Gallagher, U.S. Naval Research Laboratory
      Andrew Koehler, Naval Research Laboratory
      Mona Ebrish, NRC Postdoc Fellow Residing at the U.S. Naval Research Laboratory
      Michael Mastro, U.S. Naval Research Laboratory
      Jennifer Hite, U.S. Naval Research Laboratory
      Karl Holbart, U.S. Naval Research Laboratory

      It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

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  • Gammon, Peter

    University of Warwick
    • Correlation study between molten KOH etching and laboratory X-ray Diffraction Imaging (X-ray topography) in n+ 4H-SiC wafers

      David Jacques, Bruker UK Ltd
      Vishal Shah, University of Warwick
      Richard Bytheway, Bruker UK Ltd
      Tamzin Lafford, Bruker UK Ltd
      Benjamin Renz, University of Warwick
      Peter Gammon, University of Warwick
      Paul Ryan, Bruker UK Ltd
      Hrishikesh Das, ON Semiconductor

      In order to meet the forecast growing demand of n+ SiC material, wafer suppliers will need to implement new metrology techniques to allow the detection of crystalline defects and ensure the quality of their materials. Incumbent techniques such as KOH etching have been used for many years but remain very costly as the wafers cannot be processed further. Alternative techniques such as X-ray Diffraction Imaging (X-ray Topography) can be used to detect crystalline defects non-destructively but studies have been limited to synchrotron radiation which cannot be used as an in-line characterization. In this paper, Bruker have used novel equipment (Sensus-CS) to study the correlation between laboratory X-ray Diffraction Imaging and KOH etching performed at the University of Warwick.

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  • Gan, Kim Kok

    Bistel America Inc
    • eDataLyzer Application on Solving DS Yield Issue with Starburst Pattern

      Kim Kok Gan, Bistel America Inc
      Yiping Wang, Qorvo Inc.
      Robert Waco, Qorvo Inc.
      Matthew Johnson, Qorvo Inc.
      Pat Hamilton, Qorvo Inc.
      Jinhong Yang, Qorvo
      Dana Schwartz
      Corey Nevers, Qorvo, Inc
      Edward Elkan, Qorvo Inc.
      Kaushik Vaidyanathan, Qorvo Inc.

      A die sort (DS) yield loss forming a ‘starburst’ pattern in a wafermap was observed in a pHEMT technology manufactured by Qorvo. Typical data analysis performed by yield engineers was unable to correlate the failure root cause to a specific process step. To help drive to root cause, Bistel was consulted on the use of eDataLyzer (eDL) software.

      This paper will describe the ‘starburst’ DS yield loss pattern in details, followed by the application of Bistel’s eDL software combined with process tool Fault Detection and Correlation (FDC), and end with the validation of the failure mode.

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  • Ganjoo, Maanav

    University of Illinois, Urbana-Champaign
    • Transfer of Thin Film Gallium Phosphide onto Glass for Integrable Optical Filters

      Maanav Ganjoo, University of Illinois, Urbana-Champaign
      John Carlson, University of Illinois, Urbana-Champaign
      Saoud Al-Mulla, University of Illinois, Urbana-Champaign
      James Brown, University of Illinois, Urbana-Champaign
      Brian Cunningham, University of Illinois, Urbana-Champaign
      John Dallesasse, University of Illinois at Urbana-Chamapign

      A single-layer optical filter made from thin film gallium phosphide (GaP) is envisioned and a fabrication flow is outlined, with current progress on process development reported. Ion-implantation is simulated and performed on bulk GaP with He+, followed by a field-assisted thermal bonding technique that simultaneously bonds a thin GaP film onto a borofloat glass substrate and removes the GaP substrate. The resulting thin films have consistent thickness, both within and between runs, and RMS surface roughness of < 10 nm. Dry-etch processes that further reduce the thin film material are characterized and designs for etching gratings into them are developed. This process is shown to be a reliable means of creating thin films of consistent thickness and smoothness in GaP, for the purpose of establishing visible wavelength filters for spectroscopic applications.

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  • Gargouri, Hassan

    SENTECH Instruments GmbH
    • The influence of the GaN substrate types and the active area scaling design on the conduction properties of vertical GaN MISFETs for laser driving applications

      Joachim Würfl, Ferdinand-Braun-Institut, Berlin, Germany
      Eldad Bahat Treidel, Ferdinand-Braun-Institut, Berlin, Germany
      Oliver Hilt, Ferdinand-Braun-Institut (FBH)
      Veit Hoffman, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Frank Brunner, Ferdinand-Braun-Institut, Berlin, Germany
      Bernd Janke, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Nicole Bickel, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Hossein Yazdani, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Hassan Gargouri, SENTECH Instruments GmbH

      In this work we present a systematic study on the conduction properties in vertical GaN trench MISFETs grown and manufactured on different free standing GaN substrates. It is shown that devices manufactured on ammonothermal substrates have superior conduction current density higher than 4 kA/cm2, specific on‑state resistance as low as 1.1 ± 0.1 mWcm2 and channel sheet resistance of 19.6 ± 0.9 Wmm. It is further shown that scaling these devices to large gate periphery is not limited by current spreading in the drift region, low channel mobility or by self‑heating. The conduction properties of devices manufactured on ammonothermal GaN substrates are found to be the most suitable for pulsed laser driving applications.

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  • Geens, Karen

    imec, Leuven, Belgium
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Gemmill, William

    Eminess Technologies
    • CMP Pad Conditioning and Applications to Compound Semiconductor Wafer Processing

      Terry Knight, Eminess Technologies
      Andrew Lawing, Kinik North America
      William Gemmill, Eminess Technologies

      Pad conditioning is critical to maintaining the required process stability and performance in semiconductor CMP. As the process and performance requirements for substrate polishing in the compound semiconductor industry become more stringent, we believe there are significant opportunities for improvement via more extensive adoption of optimized pad conditioning protocols. In this paper we will review the pertinent state of the art in semiconductor CMP and propose some specific target areas for adoption in compound semiconductor substrate polishing.

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  • Gillespie, James

    Air Force Research Laboratory
    • Dispersion Characteristics of ScAlN and ScAlGaN HEMTs by Pulsed I-V Measurements

      Kelson Chabak., Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Cathy Lee, Qorvo Inc.
      Yu Cao, Raytheon IDS Microelectronics, Novati Technologies, Inc. IQE
      Andy Xie, Qorvo
      Edward Beam, QORVO
      Antonio Crespo, Air Force Research Laboratory, Sensors Directorate
      Dennis Walker, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Robert Fitch, AFRL
      James Gillespie, Air Force Research Laboratory
      Andrew Green, Air Force Research Laboratory, Sensors Directorate

      We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

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  • Green, Andrew

    Air Force Research Laboratory, Sensors Directorate
    • Self-Aligned Refractory Metal Gate Scaling in β-Ga2O3 MOSFETs

      Kelson Chabak, Air Force Research Laboratory, Sensors Directorate
      Kyle Liddy, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Andrew Green, Air Force Research Laboratory, Sensors Directorate
      Thaddeus Asel, Air Force Research Laboratory, Wright Patterson AFB, OH, USA
      Shin Mou, Air Force Research Laboratory, Wright Patterson AFB, OH
      Kevin Leedy, Air Force Research Laboratory, Sensors Directorate
      Donald Dorsey, Air Force Research Laboratory Materials and Manufacturing Directorate

      This work characterizes the effects of gate-length (LG) scaling in a self-aligned gate (SAG) β-Ga2O3 MOSFET process. Additional performance gains are expected by extending the SAG process from large LG to sub-micrometer dimensions.  This data incorporates LG scaling down to 200 nm to improve device performance in Ga2O3 SAG MOSFETs using a stepper lithography process to define sub-micron gate lengths.

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  • Green, Andrew

    Air Force Research Laboratory, Sensors Directorate
    • Dispersion Characteristics of ScAlN and ScAlGaN HEMTs by Pulsed I-V Measurements

      Kelson Chabak., Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Cathy Lee, Qorvo Inc.
      Yu Cao, Raytheon IDS Microelectronics, Novati Technologies, Inc. IQE
      Andy Xie, Qorvo
      Edward Beam, QORVO
      Antonio Crespo, Air Force Research Laboratory, Sensors Directorate
      Dennis Walker, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Robert Fitch, AFRL
      James Gillespie, Air Force Research Laboratory
      Andrew Green, Air Force Research Laboratory, Sensors Directorate

      We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

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  • Green, Malcolm

    MACOM Technology Solutions
    • Laser Diode Junction Temperature Assessment for Reliability Optimization

      Malcolm Green, MACOM Technology Solutions
      Charles Recchia, MACOM Technology Solutions
      Mark Bachman, MACOM Technology Solutions
      Lihua Hu, MACOM Technology Solutions
      Wolfgang Parz, MACOM Technology Solutions

      Determination of reliability performance over time requires an accurate understanding of device junction temperature, not only in customer use condition, but also during production test and burn-in. Through carefully designed and executed LIV (L=Light, I=current, V=Voltage) measurements and a modeling framework where optical power, thermal and electrical device parameters are interrelated, the laser diode junction temperature, as confirmed by wavelength shift measurements, is obtained via regression of a non-linear self-consistent equation.  Modeled parameters include both threshold current and slope efficiency junction linear temperature dependence coefficients/constants, as well as a thermal impedance factor.

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  • Greene, Phil

    Ferrotec Corporation
    • Development and Testing of Sub 0.5-micron Features for Advanced Lift-Off Processes

      Phil Greene, Ferrotec Corporation
      Phillip Tyler, Veeco Instruments
      Jennifer Rieker, EMD Performance Materials

      Previous studies have shown the importance of selecting the correct photoresist, metallization method, resist remover, and tool to achieve a successful lift-off[1].  Improper selection of just one of the four can result in insufficient lift-off due to conformal metal coating of the photoresist, greater number of defects, lower throughput and a higher cost of ownership.  Feature sizes of 50 µm down to 0.5 µm were previously demonstrated and this paper will focus on feature sizes under 0.5 µm.  These size features are gaining more traction in metal lift-off processes for RF and power applications that require smaller features for improved performance.

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  • Greenock, David

    X-Fab
    • Micro-scale Imaging of Electrical Activity of Yield Killer Defects in 4H-SiC with Charge Assisted KFM and UV-Photoluminescence

      Jacek Lagowski, Semilab SDI, Tampa, FL,
      Marshall Wilson, Semilab SDI, Tampa, FL,
      David Greenock, X-Fab
      Dmitriy Marinskiy, Semilab SDI, Tampa, FL,
      Alexandre Savtchouk, Semilab SDI
      Anthony Ross III, Semilab SDI
      Carlos Almeida, Semilab SDI
      Bret Schrayer, Semilab SDI, Tampa, FL,
      John D’Amico, Semilab SDI

      In this work we compare non-contact charge-voltage imaging and UV-photoluminescence (UV-PL) imaging of yield killer defects in epitaxial 4H-SiC wafers.  Two significant findings are based on macro- and micro-scale imaging, respectively.  1- Whole wafer images demonstrate that only a fraction of the UV-PL defects in triangular, downfall and carrot categories are electrically active. 2- Micro-scale images reveal similarities and differences between PL and electrical defect images.  Presented for the first time, micrometer resolution leakage patterns within triangular defects are consistent with the microstructure modeling in reference 1. The results imply that the depletion layer leakage within killer defects corresponds to exposed 3C-SiC polytypes. This leakage may be a consequence of the lower 2.2eV energy gap of 3C-SiC compared to 3.3eV in 4H-SiC.

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  • Groeseneken, Guido

    KU Leuven
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Groeseneken, Guido

    imec
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Gupta, Varun

    KLA-Tencor Limited
    • Defect Inspection for Compound Semiconductor Wafers

      Mukundkrishna Raghunathan, KLA Corporation
      Varun Gupta, KLA-Tencor Limited
      Akash Nanda, KLA Corporation

      With expanding applications and growing performance requirements in Power, RF and Optoelectronics markets, leading device manufacturers are looking for new ways to characterize yield-limiting defects that will help them achieve faster development and ramp times, higher product yields and lower device costs. Full-surface, high sensitivity defect inspection and accurate process control feedback has enabled the industry to improve substrate quality as well as to optimize the yields on epitaxy growth processes.
           As device manufacturers continue to push the boundaries of process designs, the requirements for defect inspection and overall yield management become increasingly more stringent and critical. The Candela unified surface and photoluminescence (PL) defect inspection platform enables high sensitivity inspection and defect classification at production throughputs of a wide range of critical defects (e.g. micro scratches, stacking faults, basal plane dislocations) and effectively separates front-surface defects and buried defects on transparent SiC substrates and epitaxial material. In addition, automated defect classification capabilities reduce the time required to identify, source and correct various yield-limiting defects such as carrots, triangles, sub-micron pits and others.
           The process of growing III-V epitaxy has unique challenges. The large mismatch in the lattice constant and the thermal expansion coefficient between epitaxy layer and substrate causes high lattice stress which leads to cracking on and through the epitaxy layer, making parts of the wafer unsuitable for device production. This cracking can be minimized by using a suitable buffer layer and optimizing the epitaxy reactor conditions. Improper epitaxy reactor conditions may also cause other device reliability killer defects such as micropits, craters, epi droplets and/or bumps.
           This study discusses how multiple complementary techniques such as scatterometry, reflectometry, ellipsometry and photoluminescence could be used together for simultaneous detection and classification of multiple critical defects on compound semiconductor wafers. We demonstrate how feedback from defect inspection equipment can be used to screen incoming substrate wafers and to monitor and optimize the performance of CVD reactors during the epitaxy process.

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  • Gurevich, Dimitry

    MAX I.E.G. LLC
    • Cost Reduction Opportunities in CS Maintenance & Inventory Management

      Dimitry Gurevich, MAX I.E.G. LLC
      ILIA KAPLAN, The MAX Group
      Venu Dubagunta, MAX International Engineering Group

      Major cost gaps were identified from a benchmark (BM) study for a Semiconductor fab. The study triggered deep-dive assessments of both maintenance practices and supply chain business processes. Those assessments uncovered significant improvement opportunities. In this paper, we discuss the approach used to identify and quantify those opportunities, and share important results and observations with the Compound Semiconductor (CS) manufacturing community.

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  • Guy, Owen

    Swansea University
    • Exploring the Challenges of Galiium Arsenide Plasma Dicing

      Owen Guy, Swansea University
      Will Worster, Swansea University
      Matthew Day, SPTS Technologies Limited
      M Jennings, KLA Corporation, SPTS Technologies Division, Swansea University
      Matt Elwin, Swansea University

      Plasma dicing of silicon wafers is beginning to move from pilot scale into mainstream production. Attention is now focusing on other market sectors which may benefit from a similar dicing approach.  The fragility of GaAs wafers leads to issues (such as wafer breakages, damage to die edges) during conventional wafer saw dicing. Although LASER techniques have been developed, they also have their own drawbacks – specifically sidewall quality.  A systematic investigation of the current capabilities of plasma dicing of GaAs substrates has been performed, developing technology which is both practical and economically viable. Preliminary results show smooth vertical sidewalls of trenches suitable for dicing thinned GaAs substrates at etch rates up to 23μm min-1.

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  • Haberland, Kolja

    LayTec AG
    • Advanced semiconductor metrology and process control using UV-A/UV-B LEDs

      Kolja Haberland, LayTec AG
      Kamau Prince, LayTec AG
      Volker Blank, LayTec AG
      Johannes Zettler, LayTec AG

      Traditional in-situ reflectometry sensing at blue (405 nm), red (630 nm) and NIR (950 nm) wavelengths cannot resolve variations in InAlGaN surface roughness or layer thickness with the precision necessary for effective in situ process control. LayTec has developed in situ reflectance metrology at 280 nm to address this need.

      We report successful application of in situ UV reflect-ometry and curvature, distinguishing between various phases of strain relaxation and surface relaxation during non-pseudomorphic growth of Al0.5Ga0.5N on AlN/sapphire. Results were validated by XRD, TEM and AFM. Results illuminate the influence of reduced TDD on relaxation effects during growth of UVA and UVB LED structures.

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  • Hahn, Herwig

    AIXTRON SE
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Hakone, Yoshihiro

    Nippon Kayaku Co., Ltd.
    • Low Pressure Compression Molding Demonstration on Polymer Cavity Package and Material Improvement for Thinner and Wider Cavities

      Yoshihiro Hakone, Nippon Kayaku Co., Ltd.
      Nao Honda, Nippon Kayaku Co., Ltd.
  • Hamilton, Pat

    Qorvo Inc.
    • eDataLyzer Application on Solving DS Yield Issue with Starburst Pattern

      Kim Kok Gan, Bistel America Inc
      Yiping Wang, Qorvo Inc.
      Robert Waco, Qorvo Inc.
      Matthew Johnson, Qorvo Inc.
      Pat Hamilton, Qorvo Inc.
      Jinhong Yang, Qorvo
      Dana Schwartz
      Corey Nevers, Qorvo, Inc
      Edward Elkan, Qorvo Inc.
      Kaushik Vaidyanathan, Qorvo Inc.

      A die sort (DS) yield loss forming a ‘starburst’ pattern in a wafermap was observed in a pHEMT technology manufactured by Qorvo. Typical data analysis performed by yield engineers was unable to correlate the failure root cause to a specific process step. To help drive to root cause, Bistel was consulted on the use of eDataLyzer (eDL) software.

      This paper will describe the ‘starburst’ DS yield loss pattern in details, followed by the application of Bistel’s eDL software combined with process tool Fault Detection and Correlation (FDC), and end with the validation of the failure mode.

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  • Han, Daxin

    ETH-Zürich
    • Gate Recess Etch Sensitivity of Thick and Highly-Doped GaInAs Cap Layer in InP HEMT Fabrication

      Colombo Bolognesi, ETH-Zurich
      Daxin Han, ETH-Zürich
      Diego Calvo Ruiz, ETH-Zürich
      Tamara Saranovac, ETH-Zurich
      Olivier Ostinelli, ETH-Zurich

      The use of highly-doped thick cap layers is a common strategy to enhance the performance of GaInAs/AlInAs/InP High Electron Mobility Transistors (HEMTs) by reducing the Ohmic contact resistance (RC). However, because of the high doping level, cap layers become very sensitive to processing steps performed before and during gate recess etching. In this paper, the sensitivity of gate recess etching on a 20 nm highly-doped GaInAs cap layer (doped 7.3 × 1019 cm-3) is studied with respect to Ohmic contact type (annealed/non-annealed), chip size, gate finger length, and etchant choice. The use of very high cap doping levels exacerbates device and process scaling challenges. For example, the recess finger length dependence complicates multi-project wafer runs which would simultaneously include narrow finger HEMTs used in digital ICs and longer finger HEMTs used in microwave analog circuits.

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  • Han, Min

    Wavice Inc.
    • Qualification of Wavice Baseline GaN HEMT process with 0.4 um gate on 4” SiC wafers

      Hosang Kwon, Agency for Defense Development
      Sangmin Lee, Wavice Inc.
      Byoungchul Jun, Wavice Inc.
      Chulsoon choi, Wavice Inc.
      Hyeyoung Jung, Wavice Inc.
      Seokgyu Choi, Wavice Inc.
      Min Han, Wavice Inc.
      Ho Geun Lee, Wavice Inc.
      Myoungkeun Song, Wavice Inc.
      Sung Won Lee, Wavice Inc.
      Young Jae Kim, Wavice Inc.
      Jihun Kwon, Wavice Inc.
      Myoungsoo Park, Wavice Inc.
      Sewon Hwang, Wavice Inc.
      Hangyol Ji, Wavice Inc.

      The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

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  • Hansen, Ulli

    MSG Lithoglas GmbH
    • Wafer Level Packaging for Electronic RF Systems Using GaN Technologies

      Ulli Hansen, MSG Lithoglas GmbH
      Hermann Stieglauer, United Monolithic Semiconductors GmbH
      Klaus Riepe, United Monolithic Semiconductorss GmBH
      Janina Moereke, United Monolithic Semiconductorss GmBH

      The main objective of the Covered Gallium Nitride (CoGaN) project is the demonstration of the electrical performance of a GaN HPA in a frequency range between 25 GHz and 40 GHz with a maximal output power of 5 W in a chip scale packaging technology for 5G applications. In addition, requirements are existing for reliability testing at THB condition of 85°C/85% rel. humidity. In this work a test vehicle circuit with a pre matched 1 mm transistor is used for showing the process feasibility.

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  • Hanser, Drew

    Veeco Instruments, Inc.
    • InAlN HEMT Epi and RF Devices on 8”-Si

      Huili Xing, Cornell University
      Ming Pan, Veeco Instruments
      Soo-Min Lee, Veeco Instruments
      Eric Tucker, Veeco Instruments
      Randhir Bubber, Veeco Instruments
      Ajit Paranjpe, Veeco Instruments
      Drew Hanser, Veeco Instruments, Inc.
      Kazuki Nomoto, Cornell University
      Lei Li, Cornell University
      Debdeep Jena, Cornell University

      In this paper, we report our work on epitaxial growth of InAlN HEMTs for RF device applications.  InAlN HEMTs were grown on 8” high resistivity silicon substrates. Various characterization techniques were used to analyze the quality of the epi wafers. An average sheet resistance (Rsh) of 206Ω/□, with a uniformity of 1.5% (1s/average), indicated a high quality and uniform 2DEG. Hall measurement showed a high sheet charge density of 2.27×1013cm−2 and a mobility of 1430cm2/(Vs). A pit free epi surface was obtained with optimized growth process of the active layers. T-gate RF devices fabricated on the InAlN epi wafers demonstrated an fT of 250GHz and an fMAX of 204 GHz, which are the record high values for GaN-based HEMTs on silicon.

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  • Hara, Naoki

    Fujitsu Laboratories Ltd.
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Hara, Naoki

    Fujitsu Limited
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Haung, Chong Rong

    Chang Gung University
    • The Improvement of Mg Out-diffusion in Normally-off p-GaN Gate HEMT Using Pulsed Laser Activation Technique

      Chong Rong Haung, Chang Gung University
      Hsiang-Chun Wang, Chang Gung University
      Chao-Wei Chiu, Chang Gung University

      A low- Magnesium (Mg) out-diffusion normally off p-GaN gated AlGaN/GaN high-electron-mobility transistor (HEMT) was developed using a low-temperature laser activation technique. Conventionally, during the actual p-GaN layer activation procedure, Mg out-diffuses into the AlGaN barrier and GaN channel at high temperatures. In addition, the Al of the AlGaN barrier layer is injected into GaN to generate alloy scattering and to suppress current density. In this study, the GaN doped Mg layer (Mg:GaN)was activated using short-wavelength Nd:YAG pulse laser annealing, and a conventional thermal activation device was processed for comparison. The results demonstrated that the laser activation technique in p-GaN HEMT suppressed the Mg out-diffusion-induced leakage current and trapping effect and enhanced the current density and breakdown voltage. Therefore, using this novel technique, a high and active Mg concentration and a favorable doping confinement can be obtained in the p-GaN layer to realize a stable enhancement-mode operation.

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  • Heuken, Michael

    AIXTRON SE
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Hilt, Oliver

    Ferdinand-Braun-Institut (FBH)
    • The influence of the GaN substrate types and the active area scaling design on the conduction properties of vertical GaN MISFETs for laser driving applications

      Joachim Würfl, Ferdinand-Braun-Institut, Berlin, Germany
      Eldad Bahat Treidel, Ferdinand-Braun-Institut, Berlin, Germany
      Oliver Hilt, Ferdinand-Braun-Institut (FBH)
      Veit Hoffman, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Frank Brunner, Ferdinand-Braun-Institut, Berlin, Germany
      Bernd Janke, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Nicole Bickel, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Hossein Yazdani, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Hassan Gargouri, SENTECH Instruments GmbH

      In this work we present a systematic study on the conduction properties in vertical GaN trench MISFETs grown and manufactured on different free standing GaN substrates. It is shown that devices manufactured on ammonothermal substrates have superior conduction current density higher than 4 kA/cm2, specific on‑state resistance as low as 1.1 ± 0.1 mWcm2 and channel sheet resistance of 19.6 ± 0.9 Wmm. It is further shown that scaling these devices to large gate periphery is not limited by current spreading in the drift region, low channel mobility or by self‑heating. The conduction properties of devices manufactured on ammonothermal GaN substrates are found to be the most suitable for pulsed laser driving applications.

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  • Hite, Jennifer

    U.S. Naval Research Laboratory
    • Exploring the capability of Hyperspectral Electroluminescence for process monitoring in vertical GaN devices

      Karl D. Hobart, U.S. Naval Research Laboratory
      Mona Ebrish, Vanderbilt University, Nashville, TN
      Travis J. Anderson, U.S. Naval Research Laboratory
      James Gallagher, U.S. Naval Research Laboratory
      Joseph Spencer, U.S. Naval Research Laboratory, Washington, DC, USA, Virginia Tech
      Jennifer Hite, U.S. Naval Research Laboratory
      Michael Mastro, U.S. Naval Research Laboratory

      GaN is a promising material for more efficient high frequency and high voltage power switching. However, GaN still is not the common material for power electronics due to immature substrate, homoepitaxial growth, and processing technology. Electroluminescence is a promising method to predict failure points due to high field stress, which can assist in the separation of inherent defects stemming from substrate quality, and from process-induced defects as well as identify problems related to proper edge termination design. In this work, we compare the Electroluminescence signatures of devices on inhomogeneous substrates to DC I-V behavior to demonstrate the utility of the technique for process monitoring.

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  • Hite, Jennifer

    U.S. Naval Research Laboratory
    • Predicting Vertical GaN Diode Quality using Long Range Optical tests on Substrates

      Francis Kub, U.S. Naval Research Laboratory
      James Gallagher, U.S. Naval Research Laboratory
      Andrew Koehler, Naval Research Laboratory
      Mona Ebrish, NRC Postdoc Fellow Residing at the U.S. Naval Research Laboratory
      Michael Mastro, U.S. Naval Research Laboratory
      Jennifer Hite, U.S. Naval Research Laboratory
      Karl Holbart, U.S. Naval Research Laboratory

      It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

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  • Hobart, Karl D.

    U.S. Naval Research Laboratory
    • Exploring the capability of Hyperspectral Electroluminescence for process monitoring in vertical GaN devices

      Karl D. Hobart, U.S. Naval Research Laboratory
      Mona Ebrish, Vanderbilt University, Nashville, TN
      Travis J. Anderson, U.S. Naval Research Laboratory
      James Gallagher, U.S. Naval Research Laboratory
      Joseph Spencer, U.S. Naval Research Laboratory, Washington, DC, USA, Virginia Tech
      Jennifer Hite, U.S. Naval Research Laboratory
      Michael Mastro, U.S. Naval Research Laboratory

      GaN is a promising material for more efficient high frequency and high voltage power switching. However, GaN still is not the common material for power electronics due to immature substrate, homoepitaxial growth, and processing technology. Electroluminescence is a promising method to predict failure points due to high field stress, which can assist in the separation of inherent defects stemming from substrate quality, and from process-induced defects as well as identify problems related to proper edge termination design. In this work, we compare the Electroluminescence signatures of devices on inhomogeneous substrates to DC I-V behavior to demonstrate the utility of the technique for process monitoring.

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    • Formation of Diamond Superjunctions to Enable GaN-Based Super-Lattice Power Amplifiers with Diamond Enhanced Superjunctions (SPADES)

      Geoffrey Foster, Jacobs Inc., Washington DC
      Tatyana Feygelson, Naval Research Laboratory
      James Gallagher, ASEE Postdoctoral Fellow Residing at NRL
      Josephine Chang, Northrop Grumman
      Shamima Afroz, Northrop Grumman
      Ken Nagamatsu, Northrop Grumman
      Robert Howell, Northrop Grumman
      Fritz Kub, Naval Research Laboratory

      The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

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  • Hoffman, Veit

    Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
    • The influence of the GaN substrate types and the active area scaling design on the conduction properties of vertical GaN MISFETs for laser driving applications

      Joachim Würfl, Ferdinand-Braun-Institut, Berlin, Germany
      Eldad Bahat Treidel, Ferdinand-Braun-Institut, Berlin, Germany
      Oliver Hilt, Ferdinand-Braun-Institut (FBH)
      Veit Hoffman, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Frank Brunner, Ferdinand-Braun-Institut, Berlin, Germany
      Bernd Janke, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Nicole Bickel, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Hossein Yazdani, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Hassan Gargouri, SENTECH Instruments GmbH

      In this work we present a systematic study on the conduction properties in vertical GaN trench MISFETs grown and manufactured on different free standing GaN substrates. It is shown that devices manufactured on ammonothermal substrates have superior conduction current density higher than 4 kA/cm2, specific on‑state resistance as low as 1.1 ± 0.1 mWcm2 and channel sheet resistance of 19.6 ± 0.9 Wmm. It is further shown that scaling these devices to large gate periphery is not limited by current spreading in the drift region, low channel mobility or by self‑heating. The conduction properties of devices manufactured on ammonothermal GaN substrates are found to be the most suitable for pulsed laser driving applications.

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  • Holbart, Karl

    U.S. Naval Research Laboratory
    • Predicting Vertical GaN Diode Quality using Long Range Optical tests on Substrates

      Francis Kub, U.S. Naval Research Laboratory
      James Gallagher, U.S. Naval Research Laboratory
      Andrew Koehler, Naval Research Laboratory
      Mona Ebrish, NRC Postdoc Fellow Residing at the U.S. Naval Research Laboratory
      Michael Mastro, U.S. Naval Research Laboratory
      Jennifer Hite, U.S. Naval Research Laboratory
      Karl Holbart, U.S. Naval Research Laboratory

      It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

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  • Honda, Nao

    Nippon Kayaku Co., Ltd.
    • Low Pressure Compression Molding Demonstration on Polymer Cavity Package and Material Improvement for Thinner and Wider Cavities

      Yoshihiro Hakone, Nippon Kayaku Co., Ltd.
      Nao Honda, Nippon Kayaku Co., Ltd.
  • Hore, Katie

    Oxford Instruments Plasma Technology
    • High Uniformity Etching of GaAs/AlGaAs VCSEL Mesa

      Ligang Deng, Oxford Instruments Plasma Technology
      Katie Hore, Oxford Instruments Plasma Technology
      Ning Zhang, Oxford Instruments Plasma Technology
      Stephanie Baclet, Oxford Instruments Plasma Technology

      The etching of uniform, repeatable GaAs/AlGaAs mesas is an important step in manufacturing VCSELs. This paper presents a high uniformity, low foot etching of mesa structures on 6” wafers. The improved uniformity permits the use of production-friendly optical endpoint techniques which can be used to stop on a specific layer in the VCSEL structure.

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  • Horikiri, Fumimasa

    Sciocs Company Limited
    • Fabrication of Recessed Structures for GaN HEMTs by a Simple Wet Etching Process

      Taketomo Sato, Hokkaido University
      Fumimasa Horikiri, Sciocs Company Limited
      Noboru Fukuhara, SCIOCS Company Ltd.
      Masachika Toguchi, Hokkaido University
      Kazuki Miwa, Hokkaido University
      Yoshinobu Narita, Sciocs Company Limited
      Osamu Ichikawa, SCIOCS Company Ltd.
      Ryota Isono, SCIOCS Company Ltd.
      Takeshi Tanaka, SCIOCS Company Ltd.

      Photoelectrochemical (PEC) etching is a promising technology for fabricating GaN devices with low damage. In the simple contactless PEC (CL–PEC) etching process that includes K2S2O8 in the electrolyte as an oxidizing agent, a sample is dipped into the electrolyte under UV irradiation. In this study, we applied CL–PEC to the gate-recess process of GaN HEMTs on an SiC substrate. The etching depth of the recess showed considerable reproducibility by the self-termination feature, and the residual AlGaN layer thickness was approximately 5 nm. The Schottky gate HEMTs with a recessed structure showed the normally off characteristics, and the Vth value was +0.4 V with a standard deviation of ±3.8 mV.

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  • Hosch, Michael

    United Monolithic Semiconductors
    • Impact of water content in NMP on ohmic contacts in GaN HEMT technologies

      Michael Hosch, United Monolithic Semiconductors
      Alexander Hugger, United Monolithic Semiconductors GmbH, Ulm
      Aleksandra Dlugolecka, United Monolithic Semiconductors GmbH, Ulm
      Hermann Stieglauer, United Monolithic Semiconductors Germany
      Raphael Ehrbrecht, United Monolithic Semiconductors GmbH, Ulm

      Wet chemical lift off in N-Methyl-2-pyrrolidone (NMP) is widely used in GaN HEMT Front End manufacturing.  In case of a Ti-Al-Ni-Au based metal stack for ohmic contacts, the quality of the lift-off process is much depending on the water content in the solvent NMP. In this paper, it will be shown that the metal stack can be attacked during lift off in NMP with too high water content. Additionally, environmental impacts on the hygroscopy of NMP are investigated in order to keep moisture below a certain level and avoid optical defects on ohmic contacts after lift off.

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  • Howell, Robert

    Northrop Grumman
    • Formation of Diamond Superjunctions to Enable GaN-Based Super-Lattice Power Amplifiers with Diamond Enhanced Superjunctions (SPADES)

      Geoffrey Foster, Jacobs Inc., Washington DC
      Tatyana Feygelson, Naval Research Laboratory
      James Gallagher, ASEE Postdoctoral Fellow Residing at NRL
      Josephine Chang, Northrop Grumman
      Shamima Afroz, Northrop Grumman
      Ken Nagamatsu, Northrop Grumman
      Robert Howell, Northrop Grumman
      Fritz Kub, Naval Research Laboratory

      The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

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  • Howell, Robert

    Northrop Grumman Mission Systems
    • Productization of the Superlattice Castellated Field Effect Transistor

      Justin Parke, Northrop Grumman Mission Systems
      I. Wathuthanthri, Northrop Grumman (MS), Linthicum, MD
      Ken Nagamatsu, Northrop Grumman Mission Systems
      Josephine Chang, Northrop Grumman Mission Systems
      Georges Siddiqi, HRL Laboratories
      R. Lewis, Northrop Grumman (MS), Linthicum, MD
      Robert Howell, Northrop Grumman Mission Systems

      NGMS reports the maturation of a novel GaN based 3D transistor with state of the art RF switch performance, named the SLCFET (Super Lattice Castellated Field Effect Transistor), with an RF switch FOM greater than 1.8 THz. The configured process has undergone reliability qualification for production.

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  • Howell, Robert

    Northrop Grumman Corporation
    • 100nm, Three-dimensional T-Gate for SLCFET Amplifiers

      Robert Howell, Northrop Grumman Corporation
      Annaliese Drechsler, Northrop Grumman (MS), Linthicum, MD
      Ken Nagamatsu, Northrop Grumman Corporation
      Kevin Frey, Northrop Grumman Corporation
      Monique Farrell, Northrop Grumman Corporation
      Georges Siddiqi, HRL Laboratories
      M. Scimonelli, Northrop Grumman (MS), Linthicum, MD
      Jordan Merkle, Northrop Grumman Corporation
      Josephine Chang, Northrop Grumman Corporation

      This report describes the first demonstration of a 100nm T-gate for the Superlattice Castellation Field Effect Transistor (SLCFET) amplifier. The SLCFET amplifier device utilizes a superlattice of GaN/AlGaN channels, which enables a high charge density and low source resistance. A three-dimensional T-gate structure provides electrostatic control of the channels while maintaining high gain. Improvements to the T-gate process have allowed for the scaling of the gate down to 100nm while maintaining excellent gate control, with an on to off current ratio exceeding 107. This gate scaling allows the device to reach FT / FMAX of 70/110 GHz with full passivation to maintain compatibility with the productionized SLCFET switch process.

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  • Hsiao, Fu-Chen

    University of Illinois at Urbana-Champaign
    • Design and Fabrication Considerations for Transistor-Injected Quantum Cascade Lasers for Compact, Efficient, and Controllable Mid-Wave Infrared Lasing

      John Dallesasse, University of Illinois at Urbana-Chamapign
      Robert Kaufman, University of Illinois at Urbana-Champaign
      Patrick Su, University of Illinois at Urbana-Champaign
      Fu-Chen Hsiao, University of Illinois at Urbana-Champaign

      The transistor-injected quantum cascade laser (TI-QCL) is a novel design for a mid-wave infrared (MWIR) laser that seeks to overcome some of the primary limitations of standard quantum cascade lasers (QCLs). By growing the active cascade region within the base-collector junction of an n-p-n heterojunction bipolar transistor (HBT), independent control of the injection current and active region bias is achievable through the emitter current and base-collector reverse bias respectively. The active region bias is important to properly align the lasing states and to control the lasing wavelength. Physical design limitations of the TI-QCL and their effects on the fabrication process of samples is presented. In order to characterize device performance and validate fabrication improvements, InP-based device samples designed for λ = 7.3 µm emission are fabricated. Preliminary characterization results are shown in the form of diode measurements to validate the HBT electrical operation of the TI-QCL which is necessary to realize the optical benefits of the device.

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  • Hsu, Jung-Hao

    WIN Semiconductors Corp.
    • Development of Manufacturable Commercial 6-inch InP HBT

      Cheng-Kuo Lin, WIN Semiconductors Corp
      Yu-An Liao, WIN Semiconductors Corp.
      Chun-Wei Lin, WIN Semiconductors Corp.
      Jung-Hao Hsu, WIN Semiconductors Corp.
      Shu-Hsiao Tsai, WIN Semiconductors Corp

      A foundry-ready service in 6-inch InP HBT technology has been developed for mass production in this work. Good uniformity of device performance over 6-inch wafer is obtained. Delicate EPI design with trade-off between cut-off frequency (Ft) and breakdown voltage (BVceo) are devoted to satisfy varieties of demands. We achieved Ft of 175GHz with BVceo of 6.6V and Ft of 100GHz with BVceo of 16V to fulfill the requirements in optical communication and RF power amplifier applications. An advanced sub-micron process is introduced to enhance RF performance for further demands in higher frequency region.

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  • HSU, WEN-CHING

    • The Impact of AlxGa1-xN Back Barrier in AlGaN/GaN High Electron Mobility Transistors (HEMTs) on 6-inch MCZ Si Substrate

      Yen-Lun Huang
      Hsien-Chin Chiu, Chang Gung University
      H.Y. Wang, Chang Gung University
      Chia-Hao Liu, Chang Gung University
      WEN-CHING HSU
      CHE-MING LIU
      CHIH-YUAN CHUANG
      JIA-ZHE LIU

      In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al0.08GaN) of the B.B. more strongly affected the device’ Ion/Ioff ratio. It exhibited a low leakage current and high Ion/Ioff ratio of approximately 106. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic RON. The current gain cut-off frequency (fT) and maximum stable gain cut-off frequency (fmax) were 5.2 GHz and 10.5 GHz, respectively, for the Al0.08GaN B.B. device.

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  • Hu, Lihua

    MACOM Technology Solutions
    • Laser Diode Junction Temperature Assessment for Reliability Optimization

      Malcolm Green, MACOM Technology Solutions
      Charles Recchia, MACOM Technology Solutions
      Mark Bachman, MACOM Technology Solutions
      Lihua Hu, MACOM Technology Solutions
      Wolfgang Parz, MACOM Technology Solutions

      Determination of reliability performance over time requires an accurate understanding of device junction temperature, not only in customer use condition, but also during production test and burn-in. Through carefully designed and executed LIV (L=Light, I=current, V=Voltage) measurements and a modeling framework where optical power, thermal and electrical device parameters are interrelated, the laser diode junction temperature, as confirmed by wavelength shift measurements, is obtained via regression of a non-linear self-consistent equation.  Modeled parameters include both threshold current and slope efficiency junction linear temperature dependence coefficients/constants, as well as a thermal impedance factor.

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  • Hu, Yingtao

    Hewlett Packard Labs, Hewlett Packard Enterprise
    • Heterogenious Photonic Integration by Epitaxial regrowth on Wafer Bonded Substrates

      Raymond Beausoleil, Hewlett Packard Labs, Hewlett Packard Enterprise
      Yingtao Hu, Hewlett Packard Labs, Hewlett Packard Enterprise
      Di Liang, Hewlett Packard Labs, Hewlett Packard Enterprise
      Geza Kurczveil, Hewlett Packard Labs, Hewlett Packard Enterprise

      We present a novel heterogeneous photonic integration of III/V on silicon by using epitaxial regrowth on III/V-on-Si wafer bonded substrates. This integration method decouples the correlated root causes, i.e., lattice, thermal, and domain mismatches, which are all responsible for a large number of detrimental dislocations in the heteroepitaxial process.  The grown multi-quantum well vertical p–i–n diode laser structure shows a significantly low dislocation density of 9.5 × 104 cm−2, two orders of magnitude lower than the state-of-the-art conventional monolithic growth of III/V on Si. Hybrid InP-on-Si multi-quantum well lasers were successfully demonstrated with this heterogeneous integration and shown room-temperature pulsed and continuous-wave lasing. This generic concept can be applied to other material systems to provide higher integration density, more functionalities and lower total cost for photonics as well as microelectronics, MEMS, and many other applications.

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  • Huang, Chong Rong

    Chang Gung University
    • The Characteristics of 6-inch GaN on Si RF HEMT with High Isolation Composited Buffer Layer Design

      Chong Rong Huang, Chang Gung University

      In this study, a 50-nm Al0.05Ga0.95N back barrier (BB) layer was used in an AlGaN/GaN high-electron-mobility transistor between the two-dimensional electron gas channel and Fe-doped/C-doped buffer layers. This BB layer can reduce the channel layer. The BB layer is affected by doped carriers in the buffer layer and the conduction energy band between the channel and the buffer layers. The Ion/Ioff ratio of the BB device was 3.43 × 105 and the ratio for the device without BB was 1.91 × 103. Lower leakage currents were obtained in the BB device because of the higher conduction energy band. The 0.25-μm gate length device with the BB exhibited a high current gain cutoff frequency of 26.9 GHz and power gain cutoff frequency of 54.7 GHz.

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    • The Impact of AlxGa1-xN Back Barrier in AlGaN/GaN High Electron Mobility Transistors (HEMTs) on 6-inch MCZ Si Substrate

      Yen-Lun Huang
      Hsien-Chin Chiu, Chang Gung University
      H.Y. Wang, Chang Gung University
      Chia-Hao Liu, Chang Gung University
      WEN-CHING HSU
      CHE-MING LIU
      CHIH-YUAN CHUANG
      JIA-ZHE LIU

      In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al0.08GaN) of the B.B. more strongly affected the device’ Ion/Ioff ratio. It exhibited a low leakage current and high Ion/Ioff ratio of approximately 106. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic RON. The current gain cut-off frequency (fT) and maximum stable gain cut-off frequency (fmax) were 5.2 GHz and 10.5 GHz, respectively, for the Al0.08GaN B.B. device.

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  • Huang, Yen-Lun

    • The Impact of AlxGa1-xN Back Barrier in AlGaN/GaN High Electron Mobility Transistors (HEMTs) on 6-inch MCZ Si Substrate

      Yen-Lun Huang
      Hsien-Chin Chiu, Chang Gung University
      H.Y. Wang, Chang Gung University
      Chia-Hao Liu, Chang Gung University
      WEN-CHING HSU
      CHE-MING LIU
      CHIH-YUAN CHUANG
      JIA-ZHE LIU

      In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al0.08GaN) of the B.B. more strongly affected the device’ Ion/Ioff ratio. It exhibited a low leakage current and high Ion/Ioff ratio of approximately 106. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic RON. The current gain cut-off frequency (fT) and maximum stable gain cut-off frequency (fmax) were 5.2 GHz and 10.5 GHz, respectively, for the Al0.08GaN B.B. device.

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  • Hugger, Alexander

    United Monolithic Semiconductors GmbH, Ulm
    • Impact of water content in NMP on ohmic contacts in GaN HEMT technologies

      Michael Hosch, United Monolithic Semiconductors
      Alexander Hugger, United Monolithic Semiconductors GmbH, Ulm
      Aleksandra Dlugolecka, United Monolithic Semiconductors GmbH, Ulm
      Hermann Stieglauer, United Monolithic Semiconductors Germany
      Raphael Ehrbrecht, United Monolithic Semiconductors GmbH, Ulm

      Wet chemical lift off in N-Methyl-2-pyrrolidone (NMP) is widely used in GaN HEMT Front End manufacturing.  In case of a Ti-Al-Ni-Au based metal stack for ohmic contacts, the quality of the lift-off process is much depending on the water content in the solvent NMP. In this paper, it will be shown that the metal stack can be attacked during lift off in NMP with too high water content. Additionally, environmental impacts on the hygroscopy of NMP are investigated in order to keep moisture below a certain level and avoid optical defects on ohmic contacts after lift off.

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  • Hwang, Sewon

    Wavice Inc.
    • Qualification of Wavice Baseline GaN HEMT process with 0.4 um gate on 4” SiC wafers

      Hosang Kwon, Agency for Defense Development
      Sangmin Lee, Wavice Inc.
      Byoungchul Jun, Wavice Inc.
      Chulsoon choi, Wavice Inc.
      Hyeyoung Jung, Wavice Inc.
      Seokgyu Choi, Wavice Inc.
      Min Han, Wavice Inc.
      Ho Geun Lee, Wavice Inc.
      Myoungkeun Song, Wavice Inc.
      Sung Won Lee, Wavice Inc.
      Young Jae Kim, Wavice Inc.
      Jihun Kwon, Wavice Inc.
      Myoungsoo Park, Wavice Inc.
      Sewon Hwang, Wavice Inc.
      Hangyol Ji, Wavice Inc.

      The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

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  • Ichikawa, Osamu

    SCIOCS Company Ltd.
    • Fabrication of Recessed Structures for GaN HEMTs by a Simple Wet Etching Process

      Taketomo Sato, Hokkaido University
      Fumimasa Horikiri, Sciocs Company Limited
      Noboru Fukuhara, SCIOCS Company Ltd.
      Masachika Toguchi, Hokkaido University
      Kazuki Miwa, Hokkaido University
      Yoshinobu Narita, Sciocs Company Limited
      Osamu Ichikawa, SCIOCS Company Ltd.
      Ryota Isono, SCIOCS Company Ltd.
      Takeshi Tanaka, SCIOCS Company Ltd.

      Photoelectrochemical (PEC) etching is a promising technology for fabricating GaN devices with low damage. In the simple contactless PEC (CL–PEC) etching process that includes K2S2O8 in the electrolyte as an oxidizing agent, a sample is dipped into the electrolyte under UV irradiation. In this study, we applied CL–PEC to the gate-recess process of GaN HEMTs on an SiC substrate. The etching depth of the recess showed considerable reproducibility by the self-termination feature, and the residual AlGaN layer thickness was approximately 5 nm. The Schottky gate HEMTs with a recessed structure showed the normally off characteristics, and the Vth value was +0.4 V with a standard deviation of ±3.8 mV.

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  • Isaak, Richard

    BAE Systems Inc
    • 140 nm and 90 nm GaN MMIC Technology for Millimeter-wave Power Applications

      Jose Diaz, BAE Systems Inc
      David Brown, HRL Laboratories, LLC.
      Carlton Creamer, BAE Systems Inc
      Kanin Chu, BAE Systems Inc
      Richard Isaak, BAE Systems Inc
      Louis Mt. Pleasant, BAE Systems Inc
      Donald Mitchell, BAE Systems Inc
      Puneet Srivastava, BAE Systems Inc
      Wen Zhu, BAE Systems Inc
      Hong Lu, BAE Systems Inc

      This work describes an on-going effort to develop and mature a 140 nm GaN MMIC technology with a focus on efficient power amplification at frequencies ranging from DC to 50 GHz and a 90 nm technology targeted towards V- and W-band applications, and then release the technologies within a foundry process that is open to the DoD community.

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  • Isono, Ryota

    SCIOCS Company Ltd.
    • Fabrication of Recessed Structures for GaN HEMTs by a Simple Wet Etching Process

      Taketomo Sato, Hokkaido University
      Fumimasa Horikiri, Sciocs Company Limited
      Noboru Fukuhara, SCIOCS Company Ltd.
      Masachika Toguchi, Hokkaido University
      Kazuki Miwa, Hokkaido University
      Yoshinobu Narita, Sciocs Company Limited
      Osamu Ichikawa, SCIOCS Company Ltd.
      Ryota Isono, SCIOCS Company Ltd.
      Takeshi Tanaka, SCIOCS Company Ltd.

      Photoelectrochemical (PEC) etching is a promising technology for fabricating GaN devices with low damage. In the simple contactless PEC (CL–PEC) etching process that includes K2S2O8 in the electrolyte as an oxidizing agent, a sample is dipped into the electrolyte under UV irradiation. In this study, we applied CL–PEC to the gate-recess process of GaN HEMTs on an SiC substrate. The etching depth of the recess showed considerable reproducibility by the self-termination feature, and the residual AlGaN layer thickness was approximately 5 nm. The Schottky gate HEMTs with a recessed structure showed the normally off characteristics, and the Vth value was +0.4 V with a standard deviation of ±3.8 mV.

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  • Jacques, David

    Bruker UK Ltd
    • Correlation study between molten KOH etching and laboratory X-ray Diffraction Imaging (X-ray topography) in n+ 4H-SiC wafers

      David Jacques, Bruker UK Ltd
      Vishal Shah, University of Warwick
      Richard Bytheway, Bruker UK Ltd
      Tamzin Lafford, Bruker UK Ltd
      Benjamin Renz, University of Warwick
      Peter Gammon, University of Warwick
      Paul Ryan, Bruker UK Ltd
      Hrishikesh Das, ON Semiconductor

      In order to meet the forecast growing demand of n+ SiC material, wafer suppliers will need to implement new metrology techniques to allow the detection of crystalline defects and ensure the quality of their materials. Incumbent techniques such as KOH etching have been used for many years but remain very costly as the wafers cannot be processed further. Alternative techniques such as X-ray Diffraction Imaging (X-ray Topography) can be used to detect crystalline defects non-destructively but studies have been limited to synchrotron radiation which cannot be used as an in-line characterization. In this paper, Bruker have used novel equipment (Sensus-CS) to study the correlation between laboratory X-ray Diffraction Imaging and KOH etching performed at the University of Warwick.

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  • Janke, Bernd

    Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
    • The influence of the GaN substrate types and the active area scaling design on the conduction properties of vertical GaN MISFETs for laser driving applications

      Joachim Würfl, Ferdinand-Braun-Institut, Berlin, Germany
      Eldad Bahat Treidel, Ferdinand-Braun-Institut, Berlin, Germany
      Oliver Hilt, Ferdinand-Braun-Institut (FBH)
      Veit Hoffman, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Frank Brunner, Ferdinand-Braun-Institut, Berlin, Germany
      Bernd Janke, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Nicole Bickel, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Hossein Yazdani, Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik
      Hassan Gargouri, SENTECH Instruments GmbH

      In this work we present a systematic study on the conduction properties in vertical GaN trench MISFETs grown and manufactured on different free standing GaN substrates. It is shown that devices manufactured on ammonothermal substrates have superior conduction current density higher than 4 kA/cm2, specific on‑state resistance as low as 1.1 ± 0.1 mWcm2 and channel sheet resistance of 19.6 ± 0.9 Wmm. It is further shown that scaling these devices to large gate periphery is not limited by current spreading in the drift region, low channel mobility or by self‑heating. The conduction properties of devices manufactured on ammonothermal GaN substrates are found to be the most suitable for pulsed laser driving applications.

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  • Jena, Debdeep

    Cornell University
    • InAlN HEMT Epi and RF Devices on 8”-Si

      Huili Xing, Cornell University
      Ming Pan, Veeco Instruments
      Soo-Min Lee, Veeco Instruments
      Eric Tucker, Veeco Instruments
      Randhir Bubber, Veeco Instruments
      Ajit Paranjpe, Veeco Instruments
      Drew Hanser, Veeco Instruments, Inc.
      Kazuki Nomoto, Cornell University
      Lei Li, Cornell University
      Debdeep Jena, Cornell University

      In this paper, we report our work on epitaxial growth of InAlN HEMTs for RF device applications.  InAlN HEMTs were grown on 8” high resistivity silicon substrates. Various characterization techniques were used to analyze the quality of the epi wafers. An average sheet resistance (Rsh) of 206Ω/□, with a uniformity of 1.5% (1s/average), indicated a high quality and uniform 2DEG. Hall measurement showed a high sheet charge density of 2.27×1013cm−2 and a mobility of 1430cm2/(Vs). A pit free epi surface was obtained with optimized growth process of the active layers. T-gate RF devices fabricated on the InAlN epi wafers demonstrated an fT of 250GHz and an fMAX of 204 GHz, which are the record high values for GaN-based HEMTs on silicon.

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  • Jennings, M

    KLA Corporation, SPTS Technologies Division, Swansea University
    • Exploring the Challenges of Galiium Arsenide Plasma Dicing

      Owen Guy, Swansea University
      Will Worster, Swansea University
      Matthew Day, SPTS Technologies Limited
      M Jennings, KLA Corporation, SPTS Technologies Division, Swansea University
      Matt Elwin, Swansea University

      Plasma dicing of silicon wafers is beginning to move from pilot scale into mainstream production. Attention is now focusing on other market sectors which may benefit from a similar dicing approach.  The fragility of GaAs wafers leads to issues (such as wafer breakages, damage to die edges) during conventional wafer saw dicing. Although LASER techniques have been developed, they also have their own drawbacks – specifically sidewall quality.  A systematic investigation of the current capabilities of plasma dicing of GaAs substrates has been performed, developing technology which is both practical and economically viable. Preliminary results show smooth vertical sidewalls of trenches suitable for dicing thinned GaAs substrates at etch rates up to 23μm min-1.

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  • Ji, Hangyol

    Wavice Inc.
    • Qualification of Wavice Baseline GaN HEMT process with 0.4 um gate on 4” SiC wafers

      Hosang Kwon, Agency for Defense Development
      Sangmin Lee, Wavice Inc.
      Byoungchul Jun, Wavice Inc.
      Chulsoon choi, Wavice Inc.
      Hyeyoung Jung, Wavice Inc.
      Seokgyu Choi, Wavice Inc.
      Min Han, Wavice Inc.
      Ho Geun Lee, Wavice Inc.
      Myoungkeun Song, Wavice Inc.
      Sung Won Lee, Wavice Inc.
      Young Jae Kim, Wavice Inc.
      Jihun Kwon, Wavice Inc.
      Myoungsoo Park, Wavice Inc.
      Sewon Hwang, Wavice Inc.
      Hangyol Ji, Wavice Inc.

      The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

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  • Johnson, Matthew

    Qorvo Inc.
    • eDataLyzer Application on Solving DS Yield Issue with Starburst Pattern

      Kim Kok Gan, Bistel America Inc
      Yiping Wang, Qorvo Inc.
      Robert Waco, Qorvo Inc.
      Matthew Johnson, Qorvo Inc.
      Pat Hamilton, Qorvo Inc.
      Jinhong Yang, Qorvo
      Dana Schwartz
      Corey Nevers, Qorvo, Inc
      Edward Elkan, Qorvo Inc.
      Kaushik Vaidyanathan, Qorvo Inc.

      A die sort (DS) yield loss forming a ‘starburst’ pattern in a wafermap was observed in a pHEMT technology manufactured by Qorvo. Typical data analysis performed by yield engineers was unable to correlate the failure root cause to a specific process step. To help drive to root cause, Bistel was consulted on the use of eDataLyzer (eDL) software.

      This paper will describe the ‘starburst’ DS yield loss pattern in details, followed by the application of Bistel’s eDL software combined with process tool Fault Detection and Correlation (FDC), and end with the validation of the failure mode.

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  • Johnson, Wayne

    IQE
    • RF Harmonic Distortion of Coplanar Waveguides on GaN-on-Si and GaN-on-SiC Substrates

      Patrick Fay, University of Notre Dame
      Lina Cao, Keysight Technologies
      Hansheng Ye, University of Notre Dame
      Jingshan Wang, Notre Dame
      Hugues Marchand, IQE
      Wayne Johnson, IQE

      The RF harmonic distortion of coplanar waveguides (CPWs) fabricated on AlGaN/GaN HEMT heterostructures grown on both high-resistivity Si (GaN-on-Si) and semi-insulating SiC (GaN-on-SiC) substrates is reported for the first time. The loss performance and the nonlinear behavior of the CPW lines were experimentally characterized using both small- and large-signal measurements. From 100 MHz to 20 GHz, low loss (less than 0.3 dB/mm at 20 GHz) was achieved; the attenuation of CPW lines on the GaN-on-Si substrate is ~0.05 dB/mm higher than that of the GaN-on-SiC substrate. The harmonic distortion levels of the GaN-on-Si substrate and GaN-on-SiC were also evaluated experimentally; in contrast to the small-signal loss, more significant differences in second- and third-order nonlinearity, and thus intermodulation, are observed between Si and SiC substrates. Large-signal characterization of the GaN-on-Si substrate was carried out over temperature from 25 °C to 175 °C.  Due to increases in substrate conductivity with temperature, the harmonic distortion levels are found to increase significantly at temperatures above 75 °C.

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  • Jun, Byoungchul

    Wavice Inc.
    • Qualification of Wavice Baseline GaN HEMT process with 0.4 um gate on 4” SiC wafers

      Hosang Kwon, Agency for Defense Development
      Sangmin Lee, Wavice Inc.
      Byoungchul Jun, Wavice Inc.
      Chulsoon choi, Wavice Inc.
      Hyeyoung Jung, Wavice Inc.
      Seokgyu Choi, Wavice Inc.
      Min Han, Wavice Inc.
      Ho Geun Lee, Wavice Inc.
      Myoungkeun Song, Wavice Inc.
      Sung Won Lee, Wavice Inc.
      Young Jae Kim, Wavice Inc.
      Jihun Kwon, Wavice Inc.
      Myoungsoo Park, Wavice Inc.
      Sewon Hwang, Wavice Inc.
      Hangyol Ji, Wavice Inc.

      The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

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  • Jung, Hyeyoung

    Wavice Inc.
    • Qualification of Wavice Baseline GaN HEMT process with 0.4 um gate on 4” SiC wafers

      Hosang Kwon, Agency for Defense Development
      Sangmin Lee, Wavice Inc.
      Byoungchul Jun, Wavice Inc.
      Chulsoon choi, Wavice Inc.
      Hyeyoung Jung, Wavice Inc.
      Seokgyu Choi, Wavice Inc.
      Min Han, Wavice Inc.
      Ho Geun Lee, Wavice Inc.
      Myoungkeun Song, Wavice Inc.
      Sung Won Lee, Wavice Inc.
      Young Jae Kim, Wavice Inc.
      Jihun Kwon, Wavice Inc.
      Myoungsoo Park, Wavice Inc.
      Sewon Hwang, Wavice Inc.
      Hangyol Ji, Wavice Inc.

      The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

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  • Justice, Joshua

    ON Semiconductor USA
    • P-type and N-type Channeling Ion Implantation of SiC and Implications for Device Design and Fabrication

      Takashi Kuroi, Nissin Ion Equipment Inc.
      Hrishikesh Das, ON Semiconductor USA
      Swapna Sunkari, ON Semiconductor USA
      Joshua Justice, ON Semiconductor USA
      Roman Malousek, ON Semiconductor CZ
      Jan Chochol, ON Semiconductor CZ
      Ryota Wada, Nissin Ion Equipment Inc.

      This work focuses on evaluating and demonstrating channeled p-type and n-type implantations in silicon carbide in a repeatable mass-production environment. Range increase of about 3X is observed using channeled conditions as opposed to normal incident conditions for both Aluminum and Phosphorous. The various advantages enabled by this technology for advanced device designs are highlighted. Super-junction devices targeting the same voltage range can be fabricated using 1 or 2 lesser epitaxial regrowth layers.

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  • Kaess, Felix

    IQE MA
    • SiN films grown in production scale MOCVD reactor for passivation of III-nitride structures

      Hugues Marchand, IQE MA
      Oleg Laboutin, Raytheon IDS Microelectronics, Novati Technologies, Inc. IQE
      Felix Kaess, IQE MA
      Chen-Kai Kao, IQE MA

      SiN films were grown in a production scale vertical MOCVD reactor and studied for in-situ passivation of III-nitride HEMT structures. The SiN was near-stoichiometric in composition and uniform in thickness across 4-, 6- and 8-inch diameter substrates. Its surface exhibited low roughness of about 0.3nm when the films were grown using H2 carrier gas. Contamination of the SiN with Al and Ga elements was as low as 1e16cm-3 and the H concentration was approximately 1at.% when optimized growth conditions were employed. It was demonstrated that the density of states at the SiN/III-nitride interface can be controlled by SiN growth conditions.

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  • Kaess, Felix

    IQE
    • Homoepitaxial GaN for vertical power and RF hybrid devices grown on production-scale MOCVD reactors

      Felix Kaess, IQE
      Oleg Laboutin, IQE
      Chen-Kai Kao, IQE
      Hugues Marchand, IQE

      Homoepitaxial GaN growth was implemented, studied, and improved in a production scale MOCVD reactor. The epitaxial GaN threading dislocation density was very close to that of the different free-standing GaN substrates and uniform across large diameters. We were able to limit incorporation of impurities to the low levels required for vertical electron drift layers by using appropriate growth process conditions. Different surface analysis studies revealed near-perfect step flow growth over large areas of the wafers.

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  • Kao, Chen-Kai

    IQE MA
    • SiN films grown in production scale MOCVD reactor for passivation of III-nitride structures

      Hugues Marchand, IQE MA
      Oleg Laboutin, Raytheon IDS Microelectronics, Novati Technologies, Inc. IQE
      Felix Kaess, IQE MA
      Chen-Kai Kao, IQE MA

      SiN films were grown in a production scale vertical MOCVD reactor and studied for in-situ passivation of III-nitride HEMT structures. The SiN was near-stoichiometric in composition and uniform in thickness across 4-, 6- and 8-inch diameter substrates. Its surface exhibited low roughness of about 0.3nm when the films were grown using H2 carrier gas. Contamination of the SiN with Al and Ga elements was as low as 1e16cm-3 and the H concentration was approximately 1at.% when optimized growth conditions were employed. It was demonstrated that the density of states at the SiN/III-nitride interface can be controlled by SiN growth conditions.

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  • Kao, Chen-Kai

    IQE
    • Homoepitaxial GaN for vertical power and RF hybrid devices grown on production-scale MOCVD reactors

      Felix Kaess, IQE
      Oleg Laboutin, IQE
      Chen-Kai Kao, IQE
      Hugues Marchand, IQE

      Homoepitaxial GaN growth was implemented, studied, and improved in a production scale MOCVD reactor. The epitaxial GaN threading dislocation density was very close to that of the different free-standing GaN substrates and uniform across large diameters. We were able to limit incorporation of impurities to the low levels required for vertical electron drift layers by using appropriate growth process conditions. Different surface analysis studies revealed near-perfect step flow growth over large areas of the wafers.

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  • KAPLAN, ILIA

    The MAX Group
    • Cost Reduction Opportunities in CS Maintenance & Inventory Management

      Dimitry Gurevich, MAX I.E.G. LLC
      ILIA KAPLAN, The MAX Group
      Venu Dubagunta, MAX International Engineering Group

      Major cost gaps were identified from a benchmark (BM) study for a Semiconductor fab. The study triggered deep-dive assessments of both maintenance practices and supply chain business processes. Those assessments uncovered significant improvement opportunities. In this paper, we discuss the approach used to identify and quantify those opportunities, and share important results and observations with the Compound Semiconductor (CS) manufacturing community.

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  • Katko, Maik

    Macom Technology Solutions
    • Thermal Stability, Uniformity and Electrical Properties of Sputtered and Evaporated NiCr Thin Film Resistors

      Peter Ersland, Macom Technology Solutions
      Pradeep Waduge, Macom Technology Solutions
      Maik Katko, Macom Technology Solutions
      Lisza Elliot, MACOM

      NiCr is one of the most commonly used resistive materials for fabricating precision thin film resistors due to its wide range of resistivity, low temperature coefficient of resistivity (TCR), and high stability of electrical properties. NiCr thin film resistors are usually manufactured by evaporation or sputtering. It is well known that thermal evaporation of NiCr from a finite mass of molten alloy causes a film composition change away from the composition of the source, as well as film composition changes from run to run. Some electrical properties of NiCr thin film resistors strongly depend on the film microstructure (i.e. Ni:Cr ratio) in addition to its spatial geometry (film thickness) and the deposition parameters in the evaporator. As a result, while film thickness and deposition parameters are well controlled, often time resistivity of evaporated NiCr thin film resistors goes out of spec. Therefore, in this paper we are investigating the possibility of replacing the evaporated NiCr thin films with the sputtered NiCr thin films as resistors. Here, we present a comprehensive study of NiCr thin film resistors developed using DC sputtering system and discuss the effects of sputtering process parameters and substrate conditions on film microstructure, TCR and electrical properties.

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  • Kaufman, Robert

    University of Illinois at Urbana-Champaign
    • Design and Fabrication Considerations for Transistor-Injected Quantum Cascade Lasers for Compact, Efficient, and Controllable Mid-Wave Infrared Lasing

      John Dallesasse, University of Illinois at Urbana-Chamapign
      Robert Kaufman, University of Illinois at Urbana-Champaign
      Patrick Su, University of Illinois at Urbana-Champaign
      Fu-Chen Hsiao, University of Illinois at Urbana-Champaign

      The transistor-injected quantum cascade laser (TI-QCL) is a novel design for a mid-wave infrared (MWIR) laser that seeks to overcome some of the primary limitations of standard quantum cascade lasers (QCLs). By growing the active cascade region within the base-collector junction of an n-p-n heterojunction bipolar transistor (HBT), independent control of the injection current and active region bias is achievable through the emitter current and base-collector reverse bias respectively. The active region bias is important to properly align the lasing states and to control the lasing wavelength. Physical design limitations of the TI-QCL and their effects on the fabrication process of samples is presented. In order to characterize device performance and validate fabrication improvements, InP-based device samples designed for λ = 7.3 µm emission are fabricated. Preliminary characterization results are shown in the form of diode measurements to validate the HBT electrical operation of the TI-QCL which is necessary to realize the optical benefits of the device.

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  • Keller, Stacia

    Transphorm Inc.
    • Manufacturing of N-polar GaN on Sapphire Epitaxial Wafers for Millimeter-wave Electronics Applications

      Umesh Mishra, Transphorm also Dean of Engineering UCSB
      Xiang Liu, Transphorm Inc.
      Ron Birkhahn, Transphorm Inc.
      Stacia Keller, Transphorm Inc.
      Brian Swenson, Transphorm Inc.
      Lee McCarthy, Transphorm Inc.
      Davide Bisi, Transphorm Inc.

      Transphorm is supplying N-polar GaN on SiC and sapphire epitaxial wafers for customers developing ultra-high performance RF and mm-wave electronics devices. The manufacturing process is SPC controlled and DOE optimized, and the wafers exhibit very high 2DEG electron mobility and excellent thickness and Rsh uniformities.

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  • Kim, Young Jae

    Wavice Inc.
    • Qualification of Wavice Baseline GaN HEMT process with 0.4 um gate on 4” SiC wafers

      Hosang Kwon, Agency for Defense Development
      Sangmin Lee, Wavice Inc.
      Byoungchul Jun, Wavice Inc.
      Chulsoon choi, Wavice Inc.
      Hyeyoung Jung, Wavice Inc.
      Seokgyu Choi, Wavice Inc.
      Min Han, Wavice Inc.
      Ho Geun Lee, Wavice Inc.
      Myoungkeun Song, Wavice Inc.
      Sung Won Lee, Wavice Inc.
      Young Jae Kim, Wavice Inc.
      Jihun Kwon, Wavice Inc.
      Myoungsoo Park, Wavice Inc.
      Sewon Hwang, Wavice Inc.
      Hangyol Ji, Wavice Inc.

      The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

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  • Knight, Terry

    Eminess Technologies
    • CMP Pad Conditioning and Applications to Compound Semiconductor Wafer Processing

      Terry Knight, Eminess Technologies
      Andrew Lawing, Kinik North America
      William Gemmill, Eminess Technologies

      Pad conditioning is critical to maintaining the required process stability and performance in semiconductor CMP. As the process and performance requirements for substrate polishing in the compound semiconductor industry become more stringent, we believe there are significant opportunities for improvement via more extensive adoption of optimized pad conditioning protocols. In this paper we will review the pertinent state of the art in semiconductor CMP and propose some specific target areas for adoption in compound semiconductor substrate polishing.

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  • Koehler, Andrew

    Naval Research Laboratory
    • Predicting Vertical GaN Diode Quality using Long Range Optical tests on Substrates

      Francis Kub, U.S. Naval Research Laboratory
      James Gallagher, U.S. Naval Research Laboratory
      Andrew Koehler, Naval Research Laboratory
      Mona Ebrish, NRC Postdoc Fellow Residing at the U.S. Naval Research Laboratory
      Michael Mastro, U.S. Naval Research Laboratory
      Jennifer Hite, U.S. Naval Research Laboratory
      Karl Holbart, U.S. Naval Research Laboratory

      It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

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    • Formation of Diamond Superjunctions to Enable GaN-Based Super-Lattice Power Amplifiers with Diamond Enhanced Superjunctions (SPADES)

      Geoffrey Foster, Jacobs Inc., Washington DC
      Tatyana Feygelson, Naval Research Laboratory
      James Gallagher, ASEE Postdoctoral Fellow Residing at NRL
      Josephine Chang, Northrop Grumman
      Shamima Afroz, Northrop Grumman
      Ken Nagamatsu, Northrop Grumman
      Robert Howell, Northrop Grumman
      Fritz Kub, Naval Research Laboratory

      The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

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  • Kub, Francis

    U.S. Naval Research Laboratory
    • Predicting Vertical GaN Diode Quality using Long Range Optical tests on Substrates

      Francis Kub, U.S. Naval Research Laboratory
      James Gallagher, U.S. Naval Research Laboratory
      Andrew Koehler, Naval Research Laboratory
      Mona Ebrish, NRC Postdoc Fellow Residing at the U.S. Naval Research Laboratory
      Michael Mastro, U.S. Naval Research Laboratory
      Jennifer Hite, U.S. Naval Research Laboratory
      Karl Holbart, U.S. Naval Research Laboratory

      It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

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  • Kub, Fritz

    Naval Research Laboratory
    • Formation of Diamond Superjunctions to Enable GaN-Based Super-Lattice Power Amplifiers with Diamond Enhanced Superjunctions (SPADES)

      Geoffrey Foster, Jacobs Inc., Washington DC
      Tatyana Feygelson, Naval Research Laboratory
      James Gallagher, ASEE Postdoctoral Fellow Residing at NRL
      Josephine Chang, Northrop Grumman
      Shamima Afroz, Northrop Grumman
      Ken Nagamatsu, Northrop Grumman
      Robert Howell, Northrop Grumman
      Fritz Kub, Naval Research Laboratory

      The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

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  • Kuball, Martin

    University of Bristol
    • Simulation of Leakage Induced Suppression of Bulk Dynamic RON in Power Switching GaN-on-Si HEMTs

      Martin Kuball, University of Bristol
      Michael Uren, University of Bristol
      Stefano Dalcanale, University of Bristol
      Feiyuan Yang, University of Bristol
      Ahmed Nejim, Silvaco Europe
      Stephen Wilson, Silvaco Europe

      Bulk induced dynamic RON in GaN-on-Si HEMTs is a serious performance limiting instability which remains a problem even in some commercially available power switching devices. Its origin is now reasonably well understood, however until now it has not been possible to simulate it using a realistic epitaxial stack. For the first time we successfully simulate the controlled suppression of bulk dynamic RON by adding a specific model for leakage along threading dislocations. This was undertaken using a commercially available standard TCAD simulator, allowing realistic device optimization in an advanced GaN HEMT design flow.

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  • Kuball, Matin

    University of Bristol, Bristol, UK,
    • GaN-on-diamond: the correlation between interfacial toughness and thermal resistance

      Daniel Francis, Akash Systems, San Francisco, CA, USA
      Daniel Field, University of Bristol
      Caho Yuan, University of Bristol
      Roland Simon, Thermap Solutions
      Daniel Twitchen, Element Six Technologies
      Firooz Faili, Element Six Technologies, Santa Clara, CA
      Dong Liu, University of Oxford, University of Bristol
      Matin Kuball, University of Bristol, Bristol, UK,

      A nanoindentation induced blistering method has been used to extract the GaN/diamond interfacial toughness (adhesion energy) from four types of GaN-on-diamond samples with varying SiNx interlayer thicknesses. The mode I energy release rate (GIC) was quantified and is presented. Additionally, transient thermoreflectance has been used to measure the thermal boundary resistance (TBR) between the GaN and the diamond substrate. It was found that a thin SiNx interlayer resulted in a lower TBR (15 m2 K GW-1) whilst maintaining a reasonable interfacial toughness (1.4±0.5 J m-2). For interlayers of a similar thickness, samples with a high interfacial toughness and high residual stresses in the GaN had a smaller TBR. This indicates that the intrinsic interfacial characteristics that enhanced the interfacial toughness could be beneficial in improving the TBR.

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  • Kumazaki, Yusuke

    Fujitsu Limited
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Kumazaki, Yusuke

    Fujitsu Laboratories Ltd.
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Kurczveil, Geza

    Hewlett Packard Labs, Hewlett Packard Enterprise
    • Heterogenious Photonic Integration by Epitaxial regrowth on Wafer Bonded Substrates

      Raymond Beausoleil, Hewlett Packard Labs, Hewlett Packard Enterprise
      Yingtao Hu, Hewlett Packard Labs, Hewlett Packard Enterprise
      Di Liang, Hewlett Packard Labs, Hewlett Packard Enterprise
      Geza Kurczveil, Hewlett Packard Labs, Hewlett Packard Enterprise

      We present a novel heterogeneous photonic integration of III/V on silicon by using epitaxial regrowth on III/V-on-Si wafer bonded substrates. This integration method decouples the correlated root causes, i.e., lattice, thermal, and domain mismatches, which are all responsible for a large number of detrimental dislocations in the heteroepitaxial process.  The grown multi-quantum well vertical p–i–n diode laser structure shows a significantly low dislocation density of 9.5 × 104 cm−2, two orders of magnitude lower than the state-of-the-art conventional monolithic growth of III/V on Si. Hybrid InP-on-Si multi-quantum well lasers were successfully demonstrated with this heterogeneous integration and shown room-temperature pulsed and continuous-wave lasing. This generic concept can be applied to other material systems to provide higher integration density, more functionalities and lower total cost for photonics as well as microelectronics, MEMS, and many other applications.

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  • Kurkcuoglu, Sasha

    Skyworks Solutions, Inc.
    • Methods of Improving and Optimizing Isolation Implantation for Stacked HBT on HEMT Epitaxial GaAs Semiconductor Devices

      Shiban Tiku, Skyworks Solutions, Inc.
      Sasha Kurkcuoglu, Skyworks Solutions, Inc.

      The issues of achieving good isolation and low leakage for complex integrated circuits such as stacked HBT on HEMT (BiHEMT) epitaxial GaAs semiconductor devices are described in this paper. The need for achieving a balance between short cycle time and optimum performance by use of appropriate ion implant species and schedules (energy/dose) are discussed in detail.

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  • Kuroi, Takashi

    Nissin Ion Equipment Inc.
    • P-type and N-type Channeling Ion Implantation of SiC and Implications for Device Design and Fabrication

      Takashi Kuroi, Nissin Ion Equipment Inc.
      Hrishikesh Das, ON Semiconductor USA
      Swapna Sunkari, ON Semiconductor USA
      Joshua Justice, ON Semiconductor USA
      Roman Malousek, ON Semiconductor CZ
      Jan Chochol, ON Semiconductor CZ
      Ryota Wada, Nissin Ion Equipment Inc.

      This work focuses on evaluating and demonstrating channeled p-type and n-type implantations in silicon carbide in a repeatable mass-production environment. Range increase of about 3X is observed using channeled conditions as opposed to normal incident conditions for both Aluminum and Phosphorous. The various advantages enabled by this technology for advanced device designs are highlighted. Super-junction devices targeting the same voltage range can be fabricated using 1 or 2 lesser epitaxial regrowth layers.

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  • Kwon, Hosang

    Agency for Defense Development
    • Qualification of Wavice Baseline GaN HEMT process with 0.4 um gate on 4” SiC wafers

      Hosang Kwon, Agency for Defense Development
      Sangmin Lee, Wavice Inc.
      Byoungchul Jun, Wavice Inc.
      Chulsoon choi, Wavice Inc.
      Hyeyoung Jung, Wavice Inc.
      Seokgyu Choi, Wavice Inc.
      Min Han, Wavice Inc.
      Ho Geun Lee, Wavice Inc.
      Myoungkeun Song, Wavice Inc.
      Sung Won Lee, Wavice Inc.
      Young Jae Kim, Wavice Inc.
      Jihun Kwon, Wavice Inc.
      Myoungsoo Park, Wavice Inc.
      Sewon Hwang, Wavice Inc.
      Hangyol Ji, Wavice Inc.

      The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

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  • Kwon, Jihun

    Wavice Inc.
    • Qualification of Wavice Baseline GaN HEMT process with 0.4 um gate on 4” SiC wafers

      Hosang Kwon, Agency for Defense Development
      Sangmin Lee, Wavice Inc.
      Byoungchul Jun, Wavice Inc.
      Chulsoon choi, Wavice Inc.
      Hyeyoung Jung, Wavice Inc.
      Seokgyu Choi, Wavice Inc.
      Min Han, Wavice Inc.
      Ho Geun Lee, Wavice Inc.
      Myoungkeun Song, Wavice Inc.
      Sung Won Lee, Wavice Inc.
      Young Jae Kim, Wavice Inc.
      Jihun Kwon, Wavice Inc.
      Myoungsoo Park, Wavice Inc.
      Sewon Hwang, Wavice Inc.
      Hangyol Ji, Wavice Inc.

      The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

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  • Laboutin, Oleg

    Raytheon IDS Microelectronics, Novati Technologies, Inc. IQE
    • SiN films grown in production scale MOCVD reactor for passivation of III-nitride structures

      Hugues Marchand, IQE MA
      Oleg Laboutin, Raytheon IDS Microelectronics, Novati Technologies, Inc. IQE
      Felix Kaess, IQE MA
      Chen-Kai Kao, IQE MA

      SiN films were grown in a production scale vertical MOCVD reactor and studied for in-situ passivation of III-nitride HEMT structures. The SiN was near-stoichiometric in composition and uniform in thickness across 4-, 6- and 8-inch diameter substrates. Its surface exhibited low roughness of about 0.3nm when the films were grown using H2 carrier gas. Contamination of the SiN with Al and Ga elements was as low as 1e16cm-3 and the H concentration was approximately 1at.% when optimized growth conditions were employed. It was demonstrated that the density of states at the SiN/III-nitride interface can be controlled by SiN growth conditions.

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  • Laboutin, Oleg

    IQE
    • Homoepitaxial GaN for vertical power and RF hybrid devices grown on production-scale MOCVD reactors

      Felix Kaess, IQE
      Oleg Laboutin, IQE
      Chen-Kai Kao, IQE
      Hugues Marchand, IQE

      Homoepitaxial GaN growth was implemented, studied, and improved in a production scale MOCVD reactor. The epitaxial GaN threading dislocation density was very close to that of the different free-standing GaN substrates and uniform across large diameters. We were able to limit incorporation of impurities to the low levels required for vertical electron drift layers by using appropriate growth process conditions. Different surface analysis studies revealed near-perfect step flow growth over large areas of the wafers.

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  • Lafford, Tamzin

    Bruker UK Ltd
    • Correlation study between molten KOH etching and laboratory X-ray Diffraction Imaging (X-ray topography) in n+ 4H-SiC wafers

      David Jacques, Bruker UK Ltd
      Vishal Shah, University of Warwick
      Richard Bytheway, Bruker UK Ltd
      Tamzin Lafford, Bruker UK Ltd
      Benjamin Renz, University of Warwick
      Peter Gammon, University of Warwick
      Paul Ryan, Bruker UK Ltd
      Hrishikesh Das, ON Semiconductor

      In order to meet the forecast growing demand of n+ SiC material, wafer suppliers will need to implement new metrology techniques to allow the detection of crystalline defects and ensure the quality of their materials. Incumbent techniques such as KOH etching have been used for many years but remain very costly as the wafers cannot be processed further. Alternative techniques such as X-ray Diffraction Imaging (X-ray Topography) can be used to detect crystalline defects non-destructively but studies have been limited to synchrotron radiation which cannot be used as an in-line characterization. In this paper, Bruker have used novel equipment (Sensus-CS) to study the correlation between laboratory X-ray Diffraction Imaging and KOH etching performed at the University of Warwick.

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  • Lagowski, Jacek

    Semilab SDI, Tampa, FL,
    • Micro-scale Imaging of Electrical Activity of Yield Killer Defects in 4H-SiC with Charge Assisted KFM and UV-Photoluminescence

      Jacek Lagowski, Semilab SDI, Tampa, FL,
      Marshall Wilson, Semilab SDI, Tampa, FL,
      David Greenock, X-Fab
      Dmitriy Marinskiy, Semilab SDI, Tampa, FL,
      Alexandre Savtchouk, Semilab SDI
      Anthony Ross III, Semilab SDI
      Carlos Almeida, Semilab SDI
      Bret Schrayer, Semilab SDI, Tampa, FL,
      John D’Amico, Semilab SDI

      In this work we compare non-contact charge-voltage imaging and UV-photoluminescence (UV-PL) imaging of yield killer defects in epitaxial 4H-SiC wafers.  Two significant findings are based on macro- and micro-scale imaging, respectively.  1- Whole wafer images demonstrate that only a fraction of the UV-PL defects in triangular, downfall and carrot categories are electrically active. 2- Micro-scale images reveal similarities and differences between PL and electrical defect images.  Presented for the first time, micrometer resolution leakage patterns within triangular defects are consistent with the microstructure modeling in reference 1. The results imply that the depletion layer leakage within killer defects corresponds to exposed 3C-SiC polytypes. This leakage may be a consequence of the lower 2.2eV energy gap of 3C-SiC compared to 3.3eV in 4H-SiC.

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  • Lawing, Andrew

    Kinik North America
    • CMP Pad Conditioning and Applications to Compound Semiconductor Wafer Processing

      Terry Knight, Eminess Technologies
      Andrew Lawing, Kinik North America
      William Gemmill, Eminess Technologies

      Pad conditioning is critical to maintaining the required process stability and performance in semiconductor CMP. As the process and performance requirements for substrate polishing in the compound semiconductor industry become more stringent, we believe there are significant opportunities for improvement via more extensive adoption of optimized pad conditioning protocols. In this paper we will review the pertinent state of the art in semiconductor CMP and propose some specific target areas for adoption in compound semiconductor substrate polishing.

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  • Lee, Cathy

    Qorvo Inc.
    • Dispersion Characteristics of ScAlN and ScAlGaN HEMTs by Pulsed I-V Measurements

      Kelson Chabak., Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Cathy Lee, Qorvo Inc.
      Yu Cao, Raytheon IDS Microelectronics, Novati Technologies, Inc. IQE
      Andy Xie, Qorvo
      Edward Beam, QORVO
      Antonio Crespo, Air Force Research Laboratory, Sensors Directorate
      Dennis Walker, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Robert Fitch, AFRL
      James Gillespie, Air Force Research Laboratory
      Andrew Green, Air Force Research Laboratory, Sensors Directorate

      We report the dispersion characteristics of ScAlN/GaN high-electron-mobility transistors (HEMTs) with various epitaxial designs. Devices were fabricated on both ternary (ScAlN) and quaternary (ScAlGaN) materials. The effects of a GaN capping layer was also investigated. We report similar DC and RF performance for all wafers, but significantly worse dispersion which occurs on the quaternary samples. We observe a total gate and drain lag for the ScAlN wafer to be 49% while the ScAlGaN with and without the GaN cap had 10 and 12% dispersion, respectively.

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  • Lee, Chang-Ho

    WIN Semiconductors Corp.
    • Improved Linearity GaAs pHEMT Technology and the Effect of Bias Circuit on Intermodulation Distortion Measurements

      Shuan-Ming Li, WIN Semiconductors Corp.
      Chang-Ho Lee, WIN Semiconductors Corp.
      Yong-Han Lin, WIN Semiconductors Corp.
      Sheng-Hsien Liu, WIN Semiconductors Corp.

      In this work, we present an overview of WIN’s latest generation of 0.15-mm GaAs pHEMT technology specifically optimized for highly linear PAs for advanced mm-wave communication systems. When compared with the prior technology PP15-51 at either 5.8 or 29 GHz, the new technology PP15-61 outperforms the prior one in multiple respects, including enhanced Pout, an additional linear gain of > 1 dB, a 10 percentage point increase in peak PAE (from ≈ 44% to ≈ 54% at 29 GHz), and, most notably, an improvement of ≈ 3 dB in OIP3 when operated in the linear regions at 29 GHz. As part of routine characterization, the IMD3 asymmetry was further compared for both technologies. Its behavior can be descriptively interpreted in terms of a physical scenario considering effects due to charge trapping, thermal properties, and the bias networks used in the measurements.

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  • Lee, Ho Geun

    Wavice Inc.
    • Qualification of Wavice Baseline GaN HEMT process with 0.4 um gate on 4” SiC wafers

      Hosang Kwon, Agency for Defense Development
      Sangmin Lee, Wavice Inc.
      Byoungchul Jun, Wavice Inc.
      Chulsoon choi, Wavice Inc.
      Hyeyoung Jung, Wavice Inc.
      Seokgyu Choi, Wavice Inc.
      Min Han, Wavice Inc.
      Ho Geun Lee, Wavice Inc.
      Myoungkeun Song, Wavice Inc.
      Sung Won Lee, Wavice Inc.
      Young Jae Kim, Wavice Inc.
      Jihun Kwon, Wavice Inc.
      Myoungsoo Park, Wavice Inc.
      Sewon Hwang, Wavice Inc.
      Hangyol Ji, Wavice Inc.

      The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

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  • Lee, Joe

    BISTel America
    • The Benefits of Cloud Analytics in Semiconductor – A Real-time Application Case Study

      Joe Lee, BISTel America
      Vinh Nguyen, Qorvo Richardson
      Eric McCormick, Qorvo, Inc.
      Gabe Villareal, BISTel America

      As we step into the era of Smart Manufacturing, a growing number of manufacturers across all industries are leveraging enabling technologies, such as Artificial intelligence (AI), Cloud, and Internet of Things (IOT), to help them improve productivity and profitability. Through an actual use case, this paper illustrates how one of these enabling technologies, Cloud computing, helps a semiconductor manufacturer overcome various challenges allowing them to be more productive and cost efficient.

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  • Lee, Sangmin

    Wavice Inc.
    • Qualification of Wavice Baseline GaN HEMT process with 0.4 um gate on 4” SiC wafers

      Hosang Kwon, Agency for Defense Development
      Sangmin Lee, Wavice Inc.
      Byoungchul Jun, Wavice Inc.
      Chulsoon choi, Wavice Inc.
      Hyeyoung Jung, Wavice Inc.
      Seokgyu Choi, Wavice Inc.
      Min Han, Wavice Inc.
      Ho Geun Lee, Wavice Inc.
      Myoungkeun Song, Wavice Inc.
      Sung Won Lee, Wavice Inc.
      Young Jae Kim, Wavice Inc.
      Jihun Kwon, Wavice Inc.
      Myoungsoo Park, Wavice Inc.
      Sewon Hwang, Wavice Inc.
      Hangyol Ji, Wavice Inc.

      The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

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  • Lee, Soo-Min

    Veeco Instruments
    • InAlN HEMT Epi and RF Devices on 8”-Si

      Huili Xing, Cornell University
      Ming Pan, Veeco Instruments
      Soo-Min Lee, Veeco Instruments
      Eric Tucker, Veeco Instruments
      Randhir Bubber, Veeco Instruments
      Ajit Paranjpe, Veeco Instruments
      Drew Hanser, Veeco Instruments, Inc.
      Kazuki Nomoto, Cornell University
      Lei Li, Cornell University
      Debdeep Jena, Cornell University

      In this paper, we report our work on epitaxial growth of InAlN HEMTs for RF device applications.  InAlN HEMTs were grown on 8” high resistivity silicon substrates. Various characterization techniques were used to analyze the quality of the epi wafers. An average sheet resistance (Rsh) of 206Ω/□, with a uniformity of 1.5% (1s/average), indicated a high quality and uniform 2DEG. Hall measurement showed a high sheet charge density of 2.27×1013cm−2 and a mobility of 1430cm2/(Vs). A pit free epi surface was obtained with optimized growth process of the active layers. T-gate RF devices fabricated on the InAlN epi wafers demonstrated an fT of 250GHz and an fMAX of 204 GHz, which are the record high values for GaN-based HEMTs on silicon.

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  • Lee, Sung Won

    Wavice Inc.
    • Qualification of Wavice Baseline GaN HEMT process with 0.4 um gate on 4” SiC wafers

      Hosang Kwon, Agency for Defense Development
      Sangmin Lee, Wavice Inc.
      Byoungchul Jun, Wavice Inc.
      Chulsoon choi, Wavice Inc.
      Hyeyoung Jung, Wavice Inc.
      Seokgyu Choi, Wavice Inc.
      Min Han, Wavice Inc.
      Ho Geun Lee, Wavice Inc.
      Myoungkeun Song, Wavice Inc.
      Sung Won Lee, Wavice Inc.
      Young Jae Kim, Wavice Inc.
      Jihun Kwon, Wavice Inc.
      Myoungsoo Park, Wavice Inc.
      Sewon Hwang, Wavice Inc.
      Hangyol Ji, Wavice Inc.

      The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

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  • Leedy, Kevin

    Air Force Research Laboratory, Sensors Directorate
    • Self-Aligned Refractory Metal Gate Scaling in β-Ga2O3 MOSFETs

      Kelson Chabak, Air Force Research Laboratory, Sensors Directorate
      Kyle Liddy, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Andrew Green, Air Force Research Laboratory, Sensors Directorate
      Thaddeus Asel, Air Force Research Laboratory, Wright Patterson AFB, OH, USA
      Shin Mou, Air Force Research Laboratory, Wright Patterson AFB, OH
      Kevin Leedy, Air Force Research Laboratory, Sensors Directorate
      Donald Dorsey, Air Force Research Laboratory Materials and Manufacturing Directorate

      This work characterizes the effects of gate-length (LG) scaling in a self-aligned gate (SAG) β-Ga2O3 MOSFET process. Additional performance gains are expected by extending the SAG process from large LG to sub-micrometer dimensions.  This data incorporates LG scaling down to 200 nm to improve device performance in Ga2O3 SAG MOSFETs using a stepper lithography process to define sub-micron gate lengths.

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  • Lewis, R.

    Northrop Grumman (MS), Linthicum, MD
    • Productization of the Superlattice Castellated Field Effect Transistor

      Justin Parke, Northrop Grumman Mission Systems
      I. Wathuthanthri, Northrop Grumman (MS), Linthicum, MD
      Ken Nagamatsu, Northrop Grumman Mission Systems
      Josephine Chang, Northrop Grumman Mission Systems
      Georges Siddiqi, HRL Laboratories
      R. Lewis, Northrop Grumman (MS), Linthicum, MD
      Robert Howell, Northrop Grumman Mission Systems

      NGMS reports the maturation of a novel GaN based 3D transistor with state of the art RF switch performance, named the SLCFET (Super Lattice Castellated Field Effect Transistor), with an RF switch FOM greater than 1.8 THz. The configured process has undergone reliability qualification for production.

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  • Li, Lei

    Cornell University
    • InAlN HEMT Epi and RF Devices on 8”-Si

      Huili Xing, Cornell University
      Ming Pan, Veeco Instruments
      Soo-Min Lee, Veeco Instruments
      Eric Tucker, Veeco Instruments
      Randhir Bubber, Veeco Instruments
      Ajit Paranjpe, Veeco Instruments
      Drew Hanser, Veeco Instruments, Inc.
      Kazuki Nomoto, Cornell University
      Lei Li, Cornell University
      Debdeep Jena, Cornell University

      In this paper, we report our work on epitaxial growth of InAlN HEMTs for RF device applications.  InAlN HEMTs were grown on 8” high resistivity silicon substrates. Various characterization techniques were used to analyze the quality of the epi wafers. An average sheet resistance (Rsh) of 206Ω/□, with a uniformity of 1.5% (1s/average), indicated a high quality and uniform 2DEG. Hall measurement showed a high sheet charge density of 2.27×1013cm−2 and a mobility of 1430cm2/(Vs). A pit free epi surface was obtained with optimized growth process of the active layers. T-gate RF devices fabricated on the InAlN epi wafers demonstrated an fT of 250GHz and an fMAX of 204 GHz, which are the record high values for GaN-based HEMTs on silicon.

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  • Li, Shuan-Ming

    WIN Semiconductors Corp.
    • Improved Linearity GaAs pHEMT Technology and the Effect of Bias Circuit on Intermodulation Distortion Measurements

      Shuan-Ming Li, WIN Semiconductors Corp.
      Chang-Ho Lee, WIN Semiconductors Corp.
      Yong-Han Lin, WIN Semiconductors Corp.
      Sheng-Hsien Liu, WIN Semiconductors Corp.

      In this work, we present an overview of WIN’s latest generation of 0.15-mm GaAs pHEMT technology specifically optimized for highly linear PAs for advanced mm-wave communication systems. When compared with the prior technology PP15-51 at either 5.8 or 29 GHz, the new technology PP15-61 outperforms the prior one in multiple respects, including enhanced Pout, an additional linear gain of > 1 dB, a 10 percentage point increase in peak PAE (from ≈ 44% to ≈ 54% at 29 GHz), and, most notably, an improvement of ≈ 3 dB in OIP3 when operated in the linear regions at 29 GHz. As part of routine characterization, the IMD3 asymmetry was further compared for both technologies. Its behavior can be descriptively interpreted in terms of a physical scenario considering effects due to charge trapping, thermal properties, and the bias networks used in the measurements.

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  • Li, Xiangdong

    imec
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Li, Xiangdong

    KU Leuven
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Li, Yun-Li (Charles)

    PlayNitride Display Co.
    • Development of Transparent MicroLED Display

      Ying-Tsang Liu, PlayNitride Display Co.
      Yun-Li (Charles) Li, PlayNitride Display Co.

      MicroLED is considered as the next generation display technology, since MicroLED display has high brightness, wide color gamut, high aperture ratio, and good reliability.  MicroLED display can be used for both current applications and innovative display technology. Based on our proprietary PixeLED® display technology and SMAR·TechTM repair solution, we have demonstrated high transparency borderless active-matrix MicroLED display.

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  • Liang, Di

    Hewlett Packard Labs, Hewlett Packard Enterprise
    • Heterogenious Photonic Integration by Epitaxial regrowth on Wafer Bonded Substrates

      Raymond Beausoleil, Hewlett Packard Labs, Hewlett Packard Enterprise
      Yingtao Hu, Hewlett Packard Labs, Hewlett Packard Enterprise
      Di Liang, Hewlett Packard Labs, Hewlett Packard Enterprise
      Geza Kurczveil, Hewlett Packard Labs, Hewlett Packard Enterprise

      We present a novel heterogeneous photonic integration of III/V on silicon by using epitaxial regrowth on III/V-on-Si wafer bonded substrates. This integration method decouples the correlated root causes, i.e., lattice, thermal, and domain mismatches, which are all responsible for a large number of detrimental dislocations in the heteroepitaxial process.  The grown multi-quantum well vertical p–i–n diode laser structure shows a significantly low dislocation density of 9.5 × 104 cm−2, two orders of magnitude lower than the state-of-the-art conventional monolithic growth of III/V on Si. Hybrid InP-on-Si multi-quantum well lasers were successfully demonstrated with this heterogeneous integration and shown room-temperature pulsed and continuous-wave lasing. This generic concept can be applied to other material systems to provide higher integration density, more functionalities and lower total cost for photonics as well as microelectronics, MEMS, and many other applications.

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  • Liao, Yu-An

    WIN Semiconductors Corp.
    • Development of Manufacturable Commercial 6-inch InP HBT

      Cheng-Kuo Lin, WIN Semiconductors Corp
      Yu-An Liao, WIN Semiconductors Corp.
      Chun-Wei Lin, WIN Semiconductors Corp.
      Jung-Hao Hsu, WIN Semiconductors Corp.
      Shu-Hsiao Tsai, WIN Semiconductors Corp

      A foundry-ready service in 6-inch InP HBT technology has been developed for mass production in this work. Good uniformity of device performance over 6-inch wafer is obtained. Delicate EPI design with trade-off between cut-off frequency (Ft) and breakdown voltage (BVceo) are devoted to satisfy varieties of demands. We achieved Ft of 175GHz with BVceo of 6.6V and Ft of 100GHz with BVceo of 16V to fulfill the requirements in optical communication and RF power amplifier applications. An advanced sub-micron process is introduced to enhance RF performance for further demands in higher frequency region.

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  • Liddy, Kyle

    Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
    • Self-Aligned Refractory Metal Gate Scaling in β-Ga2O3 MOSFETs

      Kelson Chabak, Air Force Research Laboratory, Sensors Directorate
      Kyle Liddy, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Andrew Green, Air Force Research Laboratory, Sensors Directorate
      Thaddeus Asel, Air Force Research Laboratory, Wright Patterson AFB, OH, USA
      Shin Mou, Air Force Research Laboratory, Wright Patterson AFB, OH
      Kevin Leedy, Air Force Research Laboratory, Sensors Directorate
      Donald Dorsey, Air Force Research Laboratory Materials and Manufacturing Directorate

      This work characterizes the effects of gate-length (LG) scaling in a self-aligned gate (SAG) β-Ga2O3 MOSFET process. Additional performance gains are expected by extending the SAG process from large LG to sub-micrometer dimensions.  This data incorporates LG scaling down to 200 nm to improve device performance in Ga2O3 SAG MOSFETs using a stepper lithography process to define sub-micron gate lengths.

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  • Lien, Yi-Wei

    WIN Semiconductors Corp
    • AlGaN/GaN Ohmic Contact Investigation

      Kai-Sin Cho, WIN Semiconductors Corp.
      Chiao-Yi Tsai, WIN Semiconductors Corp.
      Szu-Ting Chen, WIN Semiconductors Corp.
      Cheng-Ju Lin, WIN Semiconductors Corp.
      Yi-Wei Lien, WIN Semiconductors Corp
      Wei-Chou Wang, WIN Semiconductors Corp

      To produce high performance AlGaN/GaN heterostructure field effect transistors for RF power applications, one of the critical control parameters of AlGaN/GaN system is the contact resistance (Rc) of the ohmic metal to AlGaN. In the present study, two important factors for the contact resistance, a Ti3AlN interfacial layer and TiN islands were investigated using phase identification, and morphology as determined by Nano Beam Electron Diffraction (NBD) technique in transmission electron microscopy. Based on our study, both Ti3AlN interfacial layer and TiN islands contribute to ohmic contact behavior in the system.

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  • Lin, Cheng-Ju

    WIN Semiconductors Corp.
    • AlGaN/GaN Ohmic Contact Investigation

      Kai-Sin Cho, WIN Semiconductors Corp.
      Chiao-Yi Tsai, WIN Semiconductors Corp.
      Szu-Ting Chen, WIN Semiconductors Corp.
      Cheng-Ju Lin, WIN Semiconductors Corp.
      Yi-Wei Lien, WIN Semiconductors Corp
      Wei-Chou Wang, WIN Semiconductors Corp

      To produce high performance AlGaN/GaN heterostructure field effect transistors for RF power applications, one of the critical control parameters of AlGaN/GaN system is the contact resistance (Rc) of the ohmic metal to AlGaN. In the present study, two important factors for the contact resistance, a Ti3AlN interfacial layer and TiN islands were investigated using phase identification, and morphology as determined by Nano Beam Electron Diffraction (NBD) technique in transmission electron microscopy. Based on our study, both Ti3AlN interfacial layer and TiN islands contribute to ohmic contact behavior in the system.

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  • Lin, Cheng-Kuo

    WIN Semiconductors Corp
    • Development of Manufacturable Commercial 6-inch InP HBT

      Cheng-Kuo Lin, WIN Semiconductors Corp
      Yu-An Liao, WIN Semiconductors Corp.
      Chun-Wei Lin, WIN Semiconductors Corp.
      Jung-Hao Hsu, WIN Semiconductors Corp.
      Shu-Hsiao Tsai, WIN Semiconductors Corp

      A foundry-ready service in 6-inch InP HBT technology has been developed for mass production in this work. Good uniformity of device performance over 6-inch wafer is obtained. Delicate EPI design with trade-off between cut-off frequency (Ft) and breakdown voltage (BVceo) are devoted to satisfy varieties of demands. We achieved Ft of 175GHz with BVceo of 6.6V and Ft of 100GHz with BVceo of 16V to fulfill the requirements in optical communication and RF power amplifier applications. An advanced sub-micron process is introduced to enhance RF performance for further demands in higher frequency region.

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  • Lin, Chun-Wei

    WIN Semiconductors Corp.
    • Development of Manufacturable Commercial 6-inch InP HBT

      Cheng-Kuo Lin, WIN Semiconductors Corp
      Yu-An Liao, WIN Semiconductors Corp.
      Chun-Wei Lin, WIN Semiconductors Corp.
      Jung-Hao Hsu, WIN Semiconductors Corp.
      Shu-Hsiao Tsai, WIN Semiconductors Corp

      A foundry-ready service in 6-inch InP HBT technology has been developed for mass production in this work. Good uniformity of device performance over 6-inch wafer is obtained. Delicate EPI design with trade-off between cut-off frequency (Ft) and breakdown voltage (BVceo) are devoted to satisfy varieties of demands. We achieved Ft of 175GHz with BVceo of 6.6V and Ft of 100GHz with BVceo of 16V to fulfill the requirements in optical communication and RF power amplifier applications. An advanced sub-micron process is introduced to enhance RF performance for further demands in higher frequency region.

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  • LIN, Hong

    Yole Développement 75 cours Emile Zola, 69100 Villeurbanne France
    • Market opportunities for Wide-Band gap semiconductors in EV/HEV applications

      Ahmed Ben-Slimane, Yole Développement 75 cours Emile Zola, 69100 Villeurbanne France
      Hong LIN, Yole Développement 75 cours Emile Zola, 69100 Villeurbanne France
      Ezgi DOGMUS, Yole Développement

      The high growth of the EV/HEV market impacted significantly the wide bandgap semiconductor industry, creating new opportunities and a competition between SiC and GaN in many applications such as on-board chargers, DC-DC converters and main inverters. This paper provides an overview of SiC and GaN device technology, including Yole Développement’s understanding of the market’s current dynamics and future evolution of wide band gap materials compared to mainstream Silicon power electronics market.

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  • LIN, Hong

    Yole Developpement
    • Impact of high volume 3D Sensing applications on Compound Semiconductor Industry

      Pierrick Boulay, Yole Developpement
      Hong LIN, Yole Developpement
      Ahmed Ben-Slimane, Yole Developpement
      Pars Mukish, Yole Developpement
      Ezgi DOGMUS, Yole Développement
  • LIN, Hong

    Yole Developpement
    • 5G impact on Wireless Infrastructure and Compound Semiconductor Industry

      Ahmed Ben-Slimane, Yole Developpement
      Antoine Bonnabel, Yole Developpement
      Cédric MALAQUIN, Yole Developpement
      Claire Troadec, Yole Developpement
      Hong LIN, Yole Developpement
      Ezgi DOGMUS, Yole Développement

      The paper presents the market overview of different compound semiconductor such as GaN, GaAs, and InP impacted by the deployment of 5G in wireless infrastructure. The value chain from wafer and epitaxy to device level is covered, as well as technology and market trends and Yole’s forecast for the coming years.

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  • Lin, Yong-Han

    WIN Semiconductors Corp.
    • Improved Linearity GaAs pHEMT Technology and the Effect of Bias Circuit on Intermodulation Distortion Measurements

      Shuan-Ming Li, WIN Semiconductors Corp.
      Chang-Ho Lee, WIN Semiconductors Corp.
      Yong-Han Lin, WIN Semiconductors Corp.
      Sheng-Hsien Liu, WIN Semiconductors Corp.

      In this work, we present an overview of WIN’s latest generation of 0.15-mm GaAs pHEMT technology specifically optimized for highly linear PAs for advanced mm-wave communication systems. When compared with the prior technology PP15-51 at either 5.8 or 29 GHz, the new technology PP15-61 outperforms the prior one in multiple respects, including enhanced Pout, an additional linear gain of > 1 dB, a 10 percentage point increase in peak PAE (from ≈ 44% to ≈ 54% at 29 GHz), and, most notably, an improvement of ≈ 3 dB in OIP3 when operated in the linear regions at 29 GHz. As part of routine characterization, the IMD3 asymmetry was further compared for both technologies. Its behavior can be descriptively interpreted in terms of a physical scenario considering effects due to charge trapping, thermal properties, and the bias networks used in the measurements.

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  • LIU, CHE-MING

    • The Impact of AlxGa1-xN Back Barrier in AlGaN/GaN High Electron Mobility Transistors (HEMTs) on 6-inch MCZ Si Substrate

      Yen-Lun Huang
      Hsien-Chin Chiu, Chang Gung University
      H.Y. Wang, Chang Gung University
      Chia-Hao Liu, Chang Gung University
      WEN-CHING HSU
      CHE-MING LIU
      CHIH-YUAN CHUANG
      JIA-ZHE LIU

      In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al0.08GaN) of the B.B. more strongly affected the device’ Ion/Ioff ratio. It exhibited a low leakage current and high Ion/Ioff ratio of approximately 106. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic RON. The current gain cut-off frequency (fT) and maximum stable gain cut-off frequency (fmax) were 5.2 GHz and 10.5 GHz, respectively, for the Al0.08GaN B.B. device.

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  • Liu, Chia-Hao

    Chang Gung University
    • The Impact of AlxGa1-xN Back Barrier in AlGaN/GaN High Electron Mobility Transistors (HEMTs) on 6-inch MCZ Si Substrate

      Yen-Lun Huang
      Hsien-Chin Chiu, Chang Gung University
      H.Y. Wang, Chang Gung University
      Chia-Hao Liu, Chang Gung University
      WEN-CHING HSU
      CHE-MING LIU
      CHIH-YUAN CHUANG
      JIA-ZHE LIU

      In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al0.08GaN) of the B.B. more strongly affected the device’ Ion/Ioff ratio. It exhibited a low leakage current and high Ion/Ioff ratio of approximately 106. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic RON. The current gain cut-off frequency (fT) and maximum stable gain cut-off frequency (fmax) were 5.2 GHz and 10.5 GHz, respectively, for the Al0.08GaN B.B. device.

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    • The Improvement of Mg Out-diffusion in Normally-off p-GaN Gate HEMT Using Pulsed Laser Activation Technique

      Chong Rong Haung, Chang Gung University
      Hsiang-Chun Wang, Chang Gung University
      Chao-Wei Chiu, Chang Gung University

      A low- Magnesium (Mg) out-diffusion normally off p-GaN gated AlGaN/GaN high-electron-mobility transistor (HEMT) was developed using a low-temperature laser activation technique. Conventionally, during the actual p-GaN layer activation procedure, Mg out-diffuses into the AlGaN barrier and GaN channel at high temperatures. In addition, the Al of the AlGaN barrier layer is injected into GaN to generate alloy scattering and to suppress current density. In this study, the GaN doped Mg layer (Mg:GaN)was activated using short-wavelength Nd:YAG pulse laser annealing, and a conventional thermal activation device was processed for comparison. The results demonstrated that the laser activation technique in p-GaN HEMT suppressed the Mg out-diffusion-induced leakage current and trapping effect and enhanced the current density and breakdown voltage. Therefore, using this novel technique, a high and active Mg concentration and a favorable doping confinement can be obtained in the p-GaN layer to realize a stable enhancement-mode operation.

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    • High Gate Voltage Swing Region of Normally-off p-GaN MIS-HEMT  With ALD-Growth Al2O3/AlN Gate Insulator Layer

      Jin-Ping Ao, The University of Tokushima
      Chi-Chuan Chiu, Chang Gung University

      Metal–insulator–semiconductor p-type GaN high-electron-mobility transistor with an Al2O3/AlN deposited by atomic layer deposition was investigated. The selected insulator, AlN has been proven to have a good interface with GaN. A traditional p-GaN device without an Al2O3/AlN layer was processed for comparison. Due to the Al2O3/AlN layer, the gate leakage was lower, and the threshold voltage was higher, at 4.7 V. Additionally, excellent turn-on voltage was obtained. Furthermore, low current degradation and smaller VTH shift at high temperatures was also observed. Hence, growing a good-quality Al2O3/AlN layer can achieve an enhancement-mode operation with superior stability and high gate swing region.

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    • The Characteristics of 6-inch GaN on Si RF HEMT with High Isolation Composited Buffer Layer Design

      Chong Rong Huang, Chang Gung University

      In this study, a 50-nm Al0.05Ga0.95N back barrier (BB) layer was used in an AlGaN/GaN high-electron-mobility transistor between the two-dimensional electron gas channel and Fe-doped/C-doped buffer layers. This BB layer can reduce the channel layer. The BB layer is affected by doped carriers in the buffer layer and the conduction energy band between the channel and the buffer layers. The Ion/Ioff ratio of the BB device was 3.43 × 105 and the ratio for the device without BB was 1.91 × 103. Lower leakage currents were obtained in the BB device because of the higher conduction energy band. The 0.25-μm gate length device with the BB exhibited a high current gain cutoff frequency of 26.9 GHz and power gain cutoff frequency of 54.7 GHz.

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  • Liu, Dong

    University of Oxford, University of Bristol
    • GaN-on-diamond: the correlation between interfacial toughness and thermal resistance

      Daniel Francis, Akash Systems, San Francisco, CA, USA
      Daniel Field, University of Bristol
      Caho Yuan, University of Bristol
      Roland Simon, Thermap Solutions
      Daniel Twitchen, Element Six Technologies
      Firooz Faili, Element Six Technologies, Santa Clara, CA
      Dong Liu, University of Oxford, University of Bristol
      Matin Kuball, University of Bristol, Bristol, UK,

      A nanoindentation induced blistering method has been used to extract the GaN/diamond interfacial toughness (adhesion energy) from four types of GaN-on-diamond samples with varying SiNx interlayer thicknesses. The mode I energy release rate (GIC) was quantified and is presented. Additionally, transient thermoreflectance has been used to measure the thermal boundary resistance (TBR) between the GaN and the diamond substrate. It was found that a thin SiNx interlayer resulted in a lower TBR (15 m2 K GW-1) whilst maintaining a reasonable interfacial toughness (1.4±0.5 J m-2). For interlayers of a similar thickness, samples with a high interfacial toughness and high residual stresses in the GaN had a smaller TBR. This indicates that the intrinsic interfacial characteristics that enhanced the interfacial toughness could be beneficial in improving the TBR.

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  • LIU, JIA-ZHE

    • The Impact of AlxGa1-xN Back Barrier in AlGaN/GaN High Electron Mobility Transistors (HEMTs) on 6-inch MCZ Si Substrate

      Yen-Lun Huang
      Hsien-Chin Chiu, Chang Gung University
      H.Y. Wang, Chang Gung University
      Chia-Hao Liu, Chang Gung University
      WEN-CHING HSU
      CHE-MING LIU
      CHIH-YUAN CHUANG
      JIA-ZHE LIU

      In this study, AlGaN back barriers (B.B.) with different Al mole fractions and thicknesses were used in AlGaN/GaN high electron mobility transistors (HEMTs) to improve device performance. Relative to thickness, a proper Al mole fraction (Al0.08GaN) of the B.B. more strongly affected the device’ Ion/Ioff ratio. It exhibited a low leakage current and high Ion/Ioff ratio of approximately 106. Relative to B.B. mole fraction, B.B. thickness more greatly affected the devices’ horizontal breakdown voltage (760V) and LFN characteristics. Increasing the Al mole fraction and the thickness of the B.B. more strongly affected the dynamic RON. The current gain cut-off frequency (fT) and maximum stable gain cut-off frequency (fmax) were 5.2 GHz and 10.5 GHz, respectively, for the Al0.08GaN B.B. device.

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  • Liu, Sheng-Hsien

    WIN Semiconductors Corp.
    • Improved Linearity GaAs pHEMT Technology and the Effect of Bias Circuit on Intermodulation Distortion Measurements

      Shuan-Ming Li, WIN Semiconductors Corp.
      Chang-Ho Lee, WIN Semiconductors Corp.
      Yong-Han Lin, WIN Semiconductors Corp.
      Sheng-Hsien Liu, WIN Semiconductors Corp.

      In this work, we present an overview of WIN’s latest generation of 0.15-mm GaAs pHEMT technology specifically optimized for highly linear PAs for advanced mm-wave communication systems. When compared with the prior technology PP15-51 at either 5.8 or 29 GHz, the new technology PP15-61 outperforms the prior one in multiple respects, including enhanced Pout, an additional linear gain of > 1 dB, a 10 percentage point increase in peak PAE (from ≈ 44% to ≈ 54% at 29 GHz), and, most notably, an improvement of ≈ 3 dB in OIP3 when operated in the linear regions at 29 GHz. As part of routine characterization, the IMD3 asymmetry was further compared for both technologies. Its behavior can be descriptively interpreted in terms of a physical scenario considering effects due to charge trapping, thermal properties, and the bias networks used in the measurements.

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  • Liu, Xiang

    Transphorm Inc.
    • Manufacturing of N-polar GaN on Sapphire Epitaxial Wafers for Millimeter-wave Electronics Applications

      Umesh Mishra, Transphorm also Dean of Engineering UCSB
      Xiang Liu, Transphorm Inc.
      Ron Birkhahn, Transphorm Inc.
      Stacia Keller, Transphorm Inc.
      Brian Swenson, Transphorm Inc.
      Lee McCarthy, Transphorm Inc.
      Davide Bisi, Transphorm Inc.

      Transphorm is supplying N-polar GaN on SiC and sapphire epitaxial wafers for customers developing ultra-high performance RF and mm-wave electronics devices. The manufacturing process is SPC controlled and DOE optimized, and the wafers exhibit very high 2DEG electron mobility and excellent thickness and Rsh uniformities.

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  • Liu, Ying-Tsang

    PlayNitride Display Co.
    • Development of Transparent MicroLED Display

      Ying-Tsang Liu, PlayNitride Display Co.
      Yun-Li (Charles) Li, PlayNitride Display Co.

      MicroLED is considered as the next generation display technology, since MicroLED display has high brightness, wide color gamut, high aperture ratio, and good reliability.  MicroLED display can be used for both current applications and innovative display technology. Based on our proprietary PixeLED® display technology and SMAR·TechTM repair solution, we have demonstrated high transparency borderless active-matrix MicroLED display.

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  • Lu, Hong

    BAE Systems Inc
    • 140 nm and 90 nm GaN MMIC Technology for Millimeter-wave Power Applications

      Jose Diaz, BAE Systems Inc
      David Brown, HRL Laboratories, LLC.
      Carlton Creamer, BAE Systems Inc
      Kanin Chu, BAE Systems Inc
      Richard Isaak, BAE Systems Inc
      Louis Mt. Pleasant, BAE Systems Inc
      Donald Mitchell, BAE Systems Inc
      Puneet Srivastava, BAE Systems Inc
      Wen Zhu, BAE Systems Inc
      Hong Lu, BAE Systems Inc

      This work describes an on-going effort to develop and mature a 140 nm GaN MMIC technology with a focus on efficient power amplification at frequencies ranging from DC to 50 GHz and a 90 nm technology targeted towards V- and W-band applications, and then release the technologies within a foundry process that is open to the DoD community.

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  • Ma, Alex

    University of Alberta
    • Plasma Enhanced Atomic Layer Deposited Silicon Nitride on GaN MISCAPs with High Charge and Mobility

      Ken Cadien, University of Alberta
      Eric Milburn, University of Alberta
      Alex Ma, University of Alberta
      Gem Shoute, University of Alberta
      Doug Barlage, University of Alberta

      In this work fabrication of MISCAP structures was achieved on n-type gallium nitride using atomic layer deposited silicon nitride as the dielectric layer and sputtered ruthenium contacts. Preliminary values extracted from C-f data suggests very high capacitance densities up to 3.18 μF∙cm-2 and very high accumulation-mode field effect mobility, as high as 325 cm2V-1s-1 at a bias voltage of 2.5 V.

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  • Magnani, Alessandro

    imec
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Makiyama, Kozo

    Fujitsu Limited and Fujitsu Laboratories Ltd.
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Makiyama, Kozo

    Fujitsu Limited
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • MALAQUIN, Cédric

    Yole Developpement
    • 5G impact on Wireless Infrastructure and Compound Semiconductor Industry

      Ahmed Ben-Slimane, Yole Developpement
      Antoine Bonnabel, Yole Developpement
      Cédric MALAQUIN, Yole Developpement
      Claire Troadec, Yole Developpement
      Hong LIN, Yole Developpement
      Ezgi DOGMUS, Yole Développement

      The paper presents the market overview of different compound semiconductor such as GaN, GaAs, and InP impacted by the deployment of 5G in wireless infrastructure. The value chain from wafer and epitaxy to device level is covered, as well as technology and market trends and Yole’s forecast for the coming years.

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  • Malousek, Roman

    ON Semiconductor CZ
    • P-type and N-type Channeling Ion Implantation of SiC and Implications for Device Design and Fabrication

      Takashi Kuroi, Nissin Ion Equipment Inc.
      Hrishikesh Das, ON Semiconductor USA
      Swapna Sunkari, ON Semiconductor USA
      Joshua Justice, ON Semiconductor USA
      Roman Malousek, ON Semiconductor CZ
      Jan Chochol, ON Semiconductor CZ
      Ryota Wada, Nissin Ion Equipment Inc.

      This work focuses on evaluating and demonstrating channeled p-type and n-type implantations in silicon carbide in a repeatable mass-production environment. Range increase of about 3X is observed using channeled conditions as opposed to normal incident conditions for both Aluminum and Phosphorous. The various advantages enabled by this technology for advanced device designs are highlighted. Super-junction devices targeting the same voltage range can be fabricated using 1 or 2 lesser epitaxial regrowth layers.

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  • Mandracchia, Michael

    MAX International Engineering Group
    • Rapid Transformation of a Legacy Photonics Fab

      Michael Mandracchia, MAX International Engineering Group

      The MAX group was hired to provide transitional leadership and to improve fundamental performance of a legacy photonics fab. Over a six-month time-frame, weekly output increased by 32% and cycle time was cut by 46%. This paper will discuss the approach taken to transform the fab.

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  • Marchand, Hugues

    IQE MA
    • SiN films grown in production scale MOCVD reactor for passivation of III-nitride structures

      Hugues Marchand, IQE MA
      Oleg Laboutin, Raytheon IDS Microelectronics, Novati Technologies, Inc. IQE
      Felix Kaess, IQE MA
      Chen-Kai Kao, IQE MA

      SiN films were grown in a production scale vertical MOCVD reactor and studied for in-situ passivation of III-nitride HEMT structures. The SiN was near-stoichiometric in composition and uniform in thickness across 4-, 6- and 8-inch diameter substrates. Its surface exhibited low roughness of about 0.3nm when the films were grown using H2 carrier gas. Contamination of the SiN with Al and Ga elements was as low as 1e16cm-3 and the H concentration was approximately 1at.% when optimized growth conditions were employed. It was demonstrated that the density of states at the SiN/III-nitride interface can be controlled by SiN growth conditions.

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  • Marchand, Hugues

    IQE
    • Homoepitaxial GaN for vertical power and RF hybrid devices grown on production-scale MOCVD reactors

      Felix Kaess, IQE
      Oleg Laboutin, IQE
      Chen-Kai Kao, IQE
      Hugues Marchand, IQE

      Homoepitaxial GaN growth was implemented, studied, and improved in a production scale MOCVD reactor. The epitaxial GaN threading dislocation density was very close to that of the different free-standing GaN substrates and uniform across large diameters. We were able to limit incorporation of impurities to the low levels required for vertical electron drift layers by using appropriate growth process conditions. Different surface analysis studies revealed near-perfect step flow growth over large areas of the wafers.

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  • Marchand, Hugues

    IQE
    • RF Harmonic Distortion of Coplanar Waveguides on GaN-on-Si and GaN-on-SiC Substrates

      Patrick Fay, University of Notre Dame
      Lina Cao, Keysight Technologies
      Hansheng Ye, University of Notre Dame
      Jingshan Wang, Notre Dame
      Hugues Marchand, IQE
      Wayne Johnson, IQE

      The RF harmonic distortion of coplanar waveguides (CPWs) fabricated on AlGaN/GaN HEMT heterostructures grown on both high-resistivity Si (GaN-on-Si) and semi-insulating SiC (GaN-on-SiC) substrates is reported for the first time. The loss performance and the nonlinear behavior of the CPW lines were experimentally characterized using both small- and large-signal measurements. From 100 MHz to 20 GHz, low loss (less than 0.3 dB/mm at 20 GHz) was achieved; the attenuation of CPW lines on the GaN-on-Si substrate is ~0.05 dB/mm higher than that of the GaN-on-SiC substrate. The harmonic distortion levels of the GaN-on-Si substrate and GaN-on-SiC were also evaluated experimentally; in contrast to the small-signal loss, more significant differences in second- and third-order nonlinearity, and thus intermodulation, are observed between Si and SiC substrates. Large-signal characterization of the GaN-on-Si substrate was carried out over temperature from 25 °C to 175 °C.  Due to increases in substrate conductivity with temperature, the harmonic distortion levels are found to increase significantly at temperatures above 75 °C.

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  • Marcon, Denis

    imec
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Marinskiy, Dmitriy

    Semilab SDI, Tampa, FL,
    • Micro-scale Imaging of Electrical Activity of Yield Killer Defects in 4H-SiC with Charge Assisted KFM and UV-Photoluminescence

      Jacek Lagowski, Semilab SDI, Tampa, FL,
      Marshall Wilson, Semilab SDI, Tampa, FL,
      David Greenock, X-Fab
      Dmitriy Marinskiy, Semilab SDI, Tampa, FL,
      Alexandre Savtchouk, Semilab SDI
      Anthony Ross III, Semilab SDI
      Carlos Almeida, Semilab SDI
      Bret Schrayer, Semilab SDI, Tampa, FL,
      John D’Amico, Semilab SDI

      In this work we compare non-contact charge-voltage imaging and UV-photoluminescence (UV-PL) imaging of yield killer defects in epitaxial 4H-SiC wafers.  Two significant findings are based on macro- and micro-scale imaging, respectively.  1- Whole wafer images demonstrate that only a fraction of the UV-PL defects in triangular, downfall and carrot categories are electrically active. 2- Micro-scale images reveal similarities and differences between PL and electrical defect images.  Presented for the first time, micrometer resolution leakage patterns within triangular defects are consistent with the microstructure modeling in reference 1. The results imply that the depletion layer leakage within killer defects corresponds to exposed 3C-SiC polytypes. This leakage may be a consequence of the lower 2.2eV energy gap of 3C-SiC compared to 3.3eV in 4H-SiC.

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  • Maruno, Atsuki

    Samco Inc.
    • High Performance In-situ Monitoring System for ICP Dry Etching

      Tomoya Sugahara, Samco Inc.
      Shin-ichi Motoyama
      Peter Wood, SAMCO Inc.
      Atsuki Maruno, Samco Inc.

      Laser interferometric spectra and plasma emission spectra are widely used to realize precise dry etching depth control of compound semiconductor devices. However, fixed wavelength light sources for the laser interferometric systems are limited to analyze end point detection signals. Our ICP dry etching systems such as the RIE-400iP, and RIE-800iP are equipped with a high-performance in-situ monitoring system that can analyze multiple wavelengths from the reflected light of Xe or Xe-Hg (or Halogen lamp). The system is also capable of detecting the variation of plasma emission intensity simultaneously. In this work, we present examples of applying the high-performance in-situ monitoring system to GaAs, InP, and GaN-based device structure etching, and discuss the possibility of highly accurate and stable etching depth control.

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  • Mastro, Michael

    U.S. Naval Research Laboratory
    • Exploring the capability of Hyperspectral Electroluminescence for process monitoring in vertical GaN devices

      Karl D. Hobart, U.S. Naval Research Laboratory
      Mona Ebrish, Vanderbilt University, Nashville, TN
      Travis J. Anderson, U.S. Naval Research Laboratory
      James Gallagher, U.S. Naval Research Laboratory
      Joseph Spencer, U.S. Naval Research Laboratory, Washington, DC, USA, Virginia Tech
      Jennifer Hite, U.S. Naval Research Laboratory
      Michael Mastro, U.S. Naval Research Laboratory

      GaN is a promising material for more efficient high frequency and high voltage power switching. However, GaN still is not the common material for power electronics due to immature substrate, homoepitaxial growth, and processing technology. Electroluminescence is a promising method to predict failure points due to high field stress, which can assist in the separation of inherent defects stemming from substrate quality, and from process-induced defects as well as identify problems related to proper edge termination design. In this work, we compare the Electroluminescence signatures of devices on inhomogeneous substrates to DC I-V behavior to demonstrate the utility of the technique for process monitoring.

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  • Mastro, Michael

    U.S. Naval Research Laboratory
    • Predicting Vertical GaN Diode Quality using Long Range Optical tests on Substrates

      Francis Kub, U.S. Naval Research Laboratory
      James Gallagher, U.S. Naval Research Laboratory
      Andrew Koehler, Naval Research Laboratory
      Mona Ebrish, NRC Postdoc Fellow Residing at the U.S. Naval Research Laboratory
      Michael Mastro, U.S. Naval Research Laboratory
      Jennifer Hite, U.S. Naval Research Laboratory
      Karl Holbart, U.S. Naval Research Laboratory

      It is well known that vertical GaN devices could surpass current lateral GaN switch technology due to higher critical electric fields and higher breakdown voltages from its different geometry, and lower impurity concentration from the superior quality of homoepitaxial films. However, the inconsistency of GaN substrate properties, both within wafer and vendor-to-vendor, makes reliable device fabrication difficult. Here we implement long-range spectroscopic studies of GaN substrates and epitaxial wafers using Raman, photoluminescence, and optical profilometry to assess incoming material and correlate to electrical performance of vertical diodes. We have classified incoming wafers into two general types, and determined that inhomogeneities in the wafers can negatively affect the reverse leakage current of PiN diodes.

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  • Matsuyama, Hideaki

    Fuji Electric Co., Ltd.
    • Recent development of vertical GaN planar MOSFETs fabricated by Ion Implantation

      Masaharu Edo, Fuji Electric Co., Ltd.
      Ryo Tanaka, Fuji Electric Co., Ltd.
      Shinya Takashima, Fuji Electric Co., Ltd.
      Katsunori Ueno, Fuji Electric Co., Ltd.
      Hideaki Matsuyama, Fuji Electric Co., Ltd.
      Yuta Fukushima, Fuji Electric Co., Ltd.

      We have demonstrated the vertical GaN planar-gate MOSFETs fabricated by an ion implantation process.  The fabricated GaN vertical MOSFET shows a specific on-resistance of 2.78 mΩ cm2 and a breakdown voltage of 1200 V, by applying a Mg and N sequential implantation to improve the breakdown voltage of the pn-junction and the control of the MOS channel characteristics on the p-type ion implanted layer.  Consequently, the vertical GaN planar-gate MOSFETs with high breakdown voltage and low on-resistance could be realized by ion implantation process.  On the other hand, there are still many challenges for realizing practical GaN vertical MOSFETs, so continuous development is necessary.

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  • Mayer, Steven

    Skyworks Solutions, Inc
    • Reducing Lens Heating Effects on High Mileage Projection Lenses Used in Optical Lithography

      Steven Mayer, Skyworks Solutions, Inc

      The demand for low cost lithography solutions in modern manufacturing has led to extended lifetime of optical lithography equipment. Use of steppers with “high mileage” has shown that heating of the projection lens with high energy input severely degrades the aerial image. This paper discusses the lens heating effects and discusses the common solutions to address this issue. This paper also demonstrates a practical solution used in high volume manufacturing environment.
           
            This paper will discuss how absorption increases with the summation of energy through a projection lens and its effect on lens aberrations. Classical techniques to reduce lens heating effects will be presented. Low NA, low Sigma resist process, targeted for lift-off  applications, is used to study its effect on lens heating.   Solution for high transmittance, high dose application will be presented with theory, data and images.

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  • McCarthy, Lee

    Transphorm Inc.
    • Manufacturing of N-polar GaN on Sapphire Epitaxial Wafers for Millimeter-wave Electronics Applications

      Umesh Mishra, Transphorm also Dean of Engineering UCSB
      Xiang Liu, Transphorm Inc.
      Ron Birkhahn, Transphorm Inc.
      Stacia Keller, Transphorm Inc.
      Brian Swenson, Transphorm Inc.
      Lee McCarthy, Transphorm Inc.
      Davide Bisi, Transphorm Inc.

      Transphorm is supplying N-polar GaN on SiC and sapphire epitaxial wafers for customers developing ultra-high performance RF and mm-wave electronics devices. The manufacturing process is SPC controlled and DOE optimized, and the wafers exhibit very high 2DEG electron mobility and excellent thickness and Rsh uniformities.

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  • McCormick, Eric

    Qorvo, Inc.
    • The Benefits of Cloud Analytics in Semiconductor – A Real-time Application Case Study

      Joe Lee, BISTel America
      Vinh Nguyen, Qorvo Richardson
      Eric McCormick, Qorvo, Inc.
      Gabe Villareal, BISTel America

      As we step into the era of Smart Manufacturing, a growing number of manufacturers across all industries are leveraging enabling technologies, such as Artificial intelligence (AI), Cloud, and Internet of Things (IOT), to help them improve productivity and profitability. Through an actual use case, this paper illustrates how one of these enabling technologies, Cloud computing, helps a semiconductor manufacturer overcome various challenges allowing them to be more productive and cost efficient.

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  • Merkle, Jordan

    Northrop Grumman Corporation
    • 100nm, Three-dimensional T-Gate for SLCFET Amplifiers

      Robert Howell, Northrop Grumman Corporation
      Annaliese Drechsler, Northrop Grumman (MS), Linthicum, MD
      Ken Nagamatsu, Northrop Grumman Corporation
      Kevin Frey, Northrop Grumman Corporation
      Monique Farrell, Northrop Grumman Corporation
      Georges Siddiqi, HRL Laboratories
      M. Scimonelli, Northrop Grumman (MS), Linthicum, MD
      Jordan Merkle, Northrop Grumman Corporation
      Josephine Chang, Northrop Grumman Corporation

      This report describes the first demonstration of a 100nm T-gate for the Superlattice Castellation Field Effect Transistor (SLCFET) amplifier. The SLCFET amplifier device utilizes a superlattice of GaN/AlGaN channels, which enables a high charge density and low source resistance. A three-dimensional T-gate structure provides electrostatic control of the channels while maintaining high gain. Improvements to the T-gate process have allowed for the scaling of the gate down to 100nm while maintaining excellent gate control, with an on to off current ratio exceeding 107. This gate scaling allows the device to reach FT / FMAX of 70/110 GHz with full passivation to maintain compatibility with the productionized SLCFET switch process.

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  • Milburn, Eric

    University of Alberta
    • Plasma Enhanced Atomic Layer Deposited Silicon Nitride on GaN MISCAPs with High Charge and Mobility

      Ken Cadien, University of Alberta
      Eric Milburn, University of Alberta
      Alex Ma, University of Alberta
      Gem Shoute, University of Alberta
      Doug Barlage, University of Alberta

      In this work fabrication of MISCAP structures was achieved on n-type gallium nitride using atomic layer deposited silicon nitride as the dielectric layer and sputtered ruthenium contacts. Preliminary values extracted from C-f data suggests very high capacitance densities up to 3.18 μF∙cm-2 and very high accumulation-mode field effect mobility, as high as 325 cm2V-1s-1 at a bias voltage of 2.5 V.

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  • Minkoff, Moreen

    Qorvo
    • Effect of Process Variation on Pinch-Off Voltage of Depletion-Mode pHEMT

      Fred Pool, Qorvo
      Jinhong Yang, Qorvo
      Chang’e Weng, Qorvo
      Kaushik Vaidyanathan, Qorvo
      Moreen Minkoff, Qorvo
      Matthew Porter, Qorvo, Inc
      Michele Wilson, Qorvo
      Tertius River, Qorvo
      Mark Tesauro, Qorvo

      Pinch-off voltage is a key device characteristic of depletion-mode pseudomorphic high electron mobility transistors (pHEMT). Pinch-off voltage (Vp) shifts caused by manufacturing process variation were studied in this paper. Experimental results showed higher pinch-off voltage if the AlGaAs Schottky layer is oxidized or contaminated by metal. A significant increase in pinch-off voltage was observed when the Schottky layer was exposed to air for up to 2 hours after oxygen plasma treatment.  Investigation also revealed an increase in pinch-off voltage in relation to staging time and environment before gate contact metal deposition. In both cases, the effective thickness of the AlGaAs Schottky layer was reduced, and pinch-off voltage was increased. Models of metal cross-contamination and a “last wafer” effect in wet clean processing were also evaluated to address pinch-off voltage variation.

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  • Minoura, Yuichi

    Fujitsu Limited and Fujitsu Laboratories Ltd.
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Minoura, Yuichi

    Fujitsu Laboratories Ltd.
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Mishra, Umesh

    Transphorm also Dean of Engineering UCSB
    • Manufacturing of N-polar GaN on Sapphire Epitaxial Wafers for Millimeter-wave Electronics Applications

      Umesh Mishra, Transphorm also Dean of Engineering UCSB
      Xiang Liu, Transphorm Inc.
      Ron Birkhahn, Transphorm Inc.
      Stacia Keller, Transphorm Inc.
      Brian Swenson, Transphorm Inc.
      Lee McCarthy, Transphorm Inc.
      Davide Bisi, Transphorm Inc.

      Transphorm is supplying N-polar GaN on SiC and sapphire epitaxial wafers for customers developing ultra-high performance RF and mm-wave electronics devices. The manufacturing process is SPC controlled and DOE optimized, and the wafers exhibit very high 2DEG electron mobility and excellent thickness and Rsh uniformities.

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  • Mitchell, Donald

    BAE Systems Inc
    • 140 nm and 90 nm GaN MMIC Technology for Millimeter-wave Power Applications

      Jose Diaz, BAE Systems Inc
      David Brown, HRL Laboratories, LLC.
      Carlton Creamer, BAE Systems Inc
      Kanin Chu, BAE Systems Inc
      Richard Isaak, BAE Systems Inc
      Louis Mt. Pleasant, BAE Systems Inc
      Donald Mitchell, BAE Systems Inc
      Puneet Srivastava, BAE Systems Inc
      Wen Zhu, BAE Systems Inc
      Hong Lu, BAE Systems Inc

      This work describes an on-going effort to develop and mature a 140 nm GaN MMIC technology with a focus on efficient power amplification at frequencies ranging from DC to 50 GHz and a 90 nm technology targeted towards V- and W-band applications, and then release the technologies within a foundry process that is open to the DoD community.

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  • Miwa, Kazuki

    Hokkaido University
    • Fabrication of Recessed Structures for GaN HEMTs by a Simple Wet Etching Process

      Taketomo Sato, Hokkaido University
      Fumimasa Horikiri, Sciocs Company Limited
      Noboru Fukuhara, SCIOCS Company Ltd.
      Masachika Toguchi, Hokkaido University
      Kazuki Miwa, Hokkaido University
      Yoshinobu Narita, Sciocs Company Limited
      Osamu Ichikawa, SCIOCS Company Ltd.
      Ryota Isono, SCIOCS Company Ltd.
      Takeshi Tanaka, SCIOCS Company Ltd.

      Photoelectrochemical (PEC) etching is a promising technology for fabricating GaN devices with low damage. In the simple contactless PEC (CL–PEC) etching process that includes K2S2O8 in the electrolyte as an oxidizing agent, a sample is dipped into the electrolyte under UV irradiation. In this study, we applied CL–PEC to the gate-recess process of GaN HEMTs on an SiC substrate. The etching depth of the recess showed considerable reproducibility by the self-termination feature, and the residual AlGaN layer thickness was approximately 5 nm. The Schottky gate HEMTs with a recessed structure showed the normally off characteristics, and the Vth value was +0.4 V with a standard deviation of ±3.8 mV.

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  • MIYAZAKI, Hiroyuki

    CANON INC.
    • Study of new stepper solutions for various IoT devices

      Ken-Ichiro MORI, CANON INC.
      Noritoshi SAKAMOTO, CANON INC.
      Douglas SHELTON, CANON U.S.A. INC.
      Tomohiro OKAMOTO, CANON INC.
      Hiroyuki MIYAZAKI, CANON INC.

      To meet various process requirements from growing IoT devices, Canon has released FPA-3030iWa, FPA-3030i5+ and FPA-3030EX6 steppers based on the new FPA-3030 platform that is upgrade to the proven FPA-3000 stepper platform. In this paper, we will introduce FPA-3030iWa stepper solutions to support IoT device manufacturing and report evaluation data and advantages.

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  • Moereke, Janina

    United Monolithic Semiconductorss GmBH
    • Wafer Level Packaging for Electronic RF Systems Using GaN Technologies

      Ulli Hansen, MSG Lithoglas GmbH
      Hermann Stieglauer, United Monolithic Semiconductors GmbH
      Klaus Riepe, United Monolithic Semiconductorss GmBH
      Janina Moereke, United Monolithic Semiconductorss GmBH

      The main objective of the Covered Gallium Nitride (CoGaN) project is the demonstration of the electrical performance of a GaN HPA in a frequency range between 25 GHz and 40 GHz with a maximal output power of 5 W in a chip scale packaging technology for 5G applications. In addition, requirements are existing for reliability testing at THB condition of 85°C/85% rel. humidity. In this work a test vehicle circuit with a pre matched 1 mm transistor is used for showing the process feasibility.

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  • MORI, Ken-Ichiro

    CANON INC.
    • Study of new stepper solutions for various IoT devices

      Ken-Ichiro MORI, CANON INC.
      Noritoshi SAKAMOTO, CANON INC.
      Douglas SHELTON, CANON U.S.A. INC.
      Tomohiro OKAMOTO, CANON INC.
      Hiroyuki MIYAZAKI, CANON INC.

      To meet various process requirements from growing IoT devices, Canon has released FPA-3030iWa, FPA-3030i5+ and FPA-3030EX6 steppers based on the new FPA-3030 platform that is upgrade to the proven FPA-3000 stepper platform. In this paper, we will introduce FPA-3030iWa stepper solutions to support IoT device manufacturing and report evaluation data and advantages.

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  • Motoyama, Shin-ichi

    • High Performance In-situ Monitoring System for ICP Dry Etching

      Tomoya Sugahara, Samco Inc.
      Shin-ichi Motoyama
      Peter Wood, SAMCO Inc.
      Atsuki Maruno, Samco Inc.

      Laser interferometric spectra and plasma emission spectra are widely used to realize precise dry etching depth control of compound semiconductor devices. However, fixed wavelength light sources for the laser interferometric systems are limited to analyze end point detection signals. Our ICP dry etching systems such as the RIE-400iP, and RIE-800iP are equipped with a high-performance in-situ monitoring system that can analyze multiple wavelengths from the reflected light of Xe or Xe-Hg (or Halogen lamp). The system is also capable of detecting the variation of plasma emission intensity simultaneously. In this work, we present examples of applying the high-performance in-situ monitoring system to GaAs, InP, and GaN-based device structure etching, and discuss the possibility of highly accurate and stable etching depth control.

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  • Mou, Shin

    Air Force Research Laboratory, Wright Patterson AFB, OH
    • Self-Aligned Refractory Metal Gate Scaling in β-Ga2O3 MOSFETs

      Kelson Chabak, Air Force Research Laboratory, Sensors Directorate
      Kyle Liddy, Air Force Research Laboratory Sensors Directorate, WPAFB, OH, USA
      Andrew Green, Air Force Research Laboratory, Sensors Directorate
      Thaddeus Asel, Air Force Research Laboratory, Wright Patterson AFB, OH, USA
      Shin Mou, Air Force Research Laboratory, Wright Patterson AFB, OH
      Kevin Leedy, Air Force Research Laboratory, Sensors Directorate
      Donald Dorsey, Air Force Research Laboratory Materials and Manufacturing Directorate

      This work characterizes the effects of gate-length (LG) scaling in a self-aligned gate (SAG) β-Ga2O3 MOSFET process. Additional performance gains are expected by extending the SAG process from large LG to sub-micrometer dimensions.  This data incorporates LG scaling down to 200 nm to improve device performance in Ga2O3 SAG MOSFETs using a stepper lithography process to define sub-micron gate lengths.

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  • Mt. Pleasant, Louis

    BAE Systems Inc
    • 140 nm and 90 nm GaN MMIC Technology for Millimeter-wave Power Applications

      Jose Diaz, BAE Systems Inc
      David Brown, HRL Laboratories, LLC.
      Carlton Creamer, BAE Systems Inc
      Kanin Chu, BAE Systems Inc
      Richard Isaak, BAE Systems Inc
      Louis Mt. Pleasant, BAE Systems Inc
      Donald Mitchell, BAE Systems Inc
      Puneet Srivastava, BAE Systems Inc
      Wen Zhu, BAE Systems Inc
      Hong Lu, BAE Systems Inc

      This work describes an on-going effort to develop and mature a 140 nm GaN MMIC technology with a focus on efficient power amplification at frequencies ranging from DC to 50 GHz and a 90 nm technology targeted towards V- and W-band applications, and then release the technologies within a foundry process that is open to the DoD community.

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  • Mukish, Pars

    Yole Developpement
    • Impact of high volume 3D Sensing applications on Compound Semiconductor Industry

      Pierrick Boulay, Yole Developpement
      Hong LIN, Yole Developpement
      Ahmed Ben-Slimane, Yole Developpement
      Pars Mukish, Yole Developpement
      Ezgi DOGMUS, Yole Développement
  • Nabet, Bahram

    Drexel University
    • Optoplasmonic Technology for High Performing Photodetectors

      Bahram Nabet, Drexel University
      Pouya Dianat, Drexel University
      Pouya Dianat, Nanograss Photonics
      Bahram Nabet, Nanograss Photonics

      We have developed a family of opto-plasmonic devices (OPDs) for next generation Tera-bits-per-second (Tbps) tele/data communication infrastructure. Particularly, a top illuminated optical detector is produced as an essential part of the value chain in PIC. This solves a bottleneck in high-speed PIC that currently use Germanium-based photodetectors. Specifically, a photodetector is demonstrated that operates at a 6x higher bandwidth and at 10-20x lower optical power conditions, compared to a commonly used 40-GHz pin device. These provide value for optics engineers to design: i) an optical receiver module with a %75 enhancement in reliability, and ii) an optical link with 10x extension in length.

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  • Nabet, Bahram

    Nanograss Photonics
    • Optoplasmonic Technology for High Performing Photodetectors

      Bahram Nabet, Drexel University
      Pouya Dianat, Drexel University
      Pouya Dianat, Nanograss Photonics
      Bahram Nabet, Nanograss Photonics

      We have developed a family of opto-plasmonic devices (OPDs) for next generation Tera-bits-per-second (Tbps) tele/data communication infrastructure. Particularly, a top illuminated optical detector is produced as an essential part of the value chain in PIC. This solves a bottleneck in high-speed PIC that currently use Germanium-based photodetectors. Specifically, a photodetector is demonstrated that operates at a 6x higher bandwidth and at 10-20x lower optical power conditions, compared to a commonly used 40-GHz pin device. These provide value for optics engineers to design: i) an optical receiver module with a %75 enhancement in reliability, and ii) an optical link with 10x extension in length.

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  • Nagamatsu, Ken

    Northrop Grumman
    • Formation of Diamond Superjunctions to Enable GaN-Based Super-Lattice Power Amplifiers with Diamond Enhanced Superjunctions (SPADES)

      Geoffrey Foster, Jacobs Inc., Washington DC
      Tatyana Feygelson, Naval Research Laboratory
      James Gallagher, ASEE Postdoctoral Fellow Residing at NRL
      Josephine Chang, Northrop Grumman
      Shamima Afroz, Northrop Grumman
      Ken Nagamatsu, Northrop Grumman
      Robert Howell, Northrop Grumman
      Fritz Kub, Naval Research Laboratory

      The super-lattice power amplifier with diamond enhanced superjunctions (SPADES) is a device that incorporates nanocrystalline diamond superjunctions into the super-lattice castellated field effect transistor (SLCFET), to improve breakdown voltage. A diamond superjunction is formed with p-type nanocrystalline diamond to balance mutual depletion between the two-dimensional electron gas superlattices and the doped diamond in order to reduce the peak electric field in the drain access region.  Formation of the diamond superjunction presents several challenges, such as managing diamond conformality, strain, and control over p-type doping.  Optimization of diamond growth led to conformal films, with low stress, and linear dependence hole concentration from p-type doping, suitable for the SPADES device.

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  • Nagamatsu, Ken

    Northrop Grumman Mission Systems
    • Productization of the Superlattice Castellated Field Effect Transistor

      Justin Parke, Northrop Grumman Mission Systems
      I. Wathuthanthri, Northrop Grumman (MS), Linthicum, MD
      Ken Nagamatsu, Northrop Grumman Mission Systems
      Josephine Chang, Northrop Grumman Mission Systems
      Georges Siddiqi, HRL Laboratories
      R. Lewis, Northrop Grumman (MS), Linthicum, MD
      Robert Howell, Northrop Grumman Mission Systems

      NGMS reports the maturation of a novel GaN based 3D transistor with state of the art RF switch performance, named the SLCFET (Super Lattice Castellated Field Effect Transistor), with an RF switch FOM greater than 1.8 THz. The configured process has undergone reliability qualification for production.

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  • Nagamatsu, Ken

    Northrop Grumman Corporation
    • 100nm, Three-dimensional T-Gate for SLCFET Amplifiers

      Robert Howell, Northrop Grumman Corporation
      Annaliese Drechsler, Northrop Grumman (MS), Linthicum, MD
      Ken Nagamatsu, Northrop Grumman Corporation
      Kevin Frey, Northrop Grumman Corporation
      Monique Farrell, Northrop Grumman Corporation
      Georges Siddiqi, HRL Laboratories
      M. Scimonelli, Northrop Grumman (MS), Linthicum, MD
      Jordan Merkle, Northrop Grumman Corporation
      Josephine Chang, Northrop Grumman Corporation

      This report describes the first demonstration of a 100nm T-gate for the Superlattice Castellation Field Effect Transistor (SLCFET) amplifier. The SLCFET amplifier device utilizes a superlattice of GaN/AlGaN channels, which enables a high charge density and low source resistance. A three-dimensional T-gate structure provides electrostatic control of the channels while maintaining high gain. Improvements to the T-gate process have allowed for the scaling of the gate down to 100nm while maintaining excellent gate control, with an on to off current ratio exceeding 107. This gate scaling allows the device to reach FT / FMAX of 70/110 GHz with full passivation to maintain compatibility with the productionized SLCFET switch process.

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  • Nakamura, Norikazu

    Fujitsu Limited and Fujitsu Laboratories Ltd.
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Nanda, Akash

    KLA Corporation
    • Defect Inspection for Compound Semiconductor Wafers

      Mukundkrishna Raghunathan, KLA Corporation
      Varun Gupta, KLA-Tencor Limited
      Akash Nanda, KLA Corporation

      With expanding applications and growing performance requirements in Power, RF and Optoelectronics markets, leading device manufacturers are looking for new ways to characterize yield-limiting defects that will help them achieve faster development and ramp times, higher product yields and lower device costs. Full-surface, high sensitivity defect inspection and accurate process control feedback has enabled the industry to improve substrate quality as well as to optimize the yields on epitaxy growth processes.
           As device manufacturers continue to push the boundaries of process designs, the requirements for defect inspection and overall yield management become increasingly more stringent and critical. The Candela unified surface and photoluminescence (PL) defect inspection platform enables high sensitivity inspection and defect classification at production throughputs of a wide range of critical defects (e.g. micro scratches, stacking faults, basal plane dislocations) and effectively separates front-surface defects and buried defects on transparent SiC substrates and epitaxial material. In addition, automated defect classification capabilities reduce the time required to identify, source and correct various yield-limiting defects such as carrots, triangles, sub-micron pits and others.
           The process of growing III-V epitaxy has unique challenges. The large mismatch in the lattice constant and the thermal expansion coefficient between epitaxy layer and substrate causes high lattice stress which leads to cracking on and through the epitaxy layer, making parts of the wafer unsuitable for device production. This cracking can be minimized by using a suitable buffer layer and optimizing the epitaxy reactor conditions. Improper epitaxy reactor conditions may also cause other device reliability killer defects such as micropits, craters, epi droplets and/or bumps.
           This study discusses how multiple complementary techniques such as scatterometry, reflectometry, ellipsometry and photoluminescence could be used together for simultaneous detection and classification of multiple critical defects on compound semiconductor wafers. We demonstrate how feedback from defect inspection equipment can be used to screen incoming substrate wafers and to monitor and optimize the performance of CVD reactors during the epitaxy process.

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  • Narita, Yoshinobu

    Sciocs Company Limited
    • Fabrication of Recessed Structures for GaN HEMTs by a Simple Wet Etching Process

      Taketomo Sato, Hokkaido University
      Fumimasa Horikiri, Sciocs Company Limited
      Noboru Fukuhara, SCIOCS Company Ltd.
      Masachika Toguchi, Hokkaido University
      Kazuki Miwa, Hokkaido University
      Yoshinobu Narita, Sciocs Company Limited
      Osamu Ichikawa, SCIOCS Company Ltd.
      Ryota Isono, SCIOCS Company Ltd.
      Takeshi Tanaka, SCIOCS Company Ltd.

      Photoelectrochemical (PEC) etching is a promising technology for fabricating GaN devices with low damage. In the simple contactless PEC (CL–PEC) etching process that includes K2S2O8 in the electrolyte as an oxidizing agent, a sample is dipped into the electrolyte under UV irradiation. In this study, we applied CL–PEC to the gate-recess process of GaN HEMTs on an SiC substrate. The etching depth of the recess showed considerable reproducibility by the self-termination feature, and the residual AlGaN layer thickness was approximately 5 nm. The Schottky gate HEMTs with a recessed structure showed the normally off characteristics, and the Vth value was +0.4 V with a standard deviation of ±3.8 mV.

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  • Nawrocki, Dan

    Kayaku Advanced Materials
    • Optimizing Bi-layer Lift-off Resist Processes for Insulator Films

      Lori Rattray, Kayaku Advanced Materials
      Robert Wadja, Kayaku Advanced Materials
      Dan Nawrocki, Kayaku Advanced Materials

      The bi-layer lift-off method has been used successfully to commercially fabricate many structures including source, drain ohmic contacts, gates and air bridges for use in Gallium Arsenide (GaAs), GaN, InP, MEMS and other semiconductor devices.  It is widely adopted for common pattern metallization processes.  The process utilizes LOR-PMGI (polydimethylglutarimide) plus an imaging resist to create a dual layer masking structure.  Uniquely, this structure can be customized because its composition and dimensions can be tailored for a given material-deposition-application system. This is enabling for use in select process applications.

      Deployment of VCSEL applications enabled by 5G latency advantages can benefit by using commercialized technology to comply industry development clockspeed.[1]  VCSEL devices can be broadly categorized in terms of deposition material thicknesses and structures based on power output.[2]  This study quantifies the most relevant bi-layer structural features for effective use with the reference metallization film, Aluminum.  It builds on these findings to explore the multivariate optimization required to successfully use bi-layer processing with common metal oxide insulators (SiO2 / Al2O3) in isotropically sputter deposited thicknesses of 100nm to 250nm.  A model is presented that characterizes the key variables.  Also, it introduces a new high temperature bi-layer process using a negative imaging resist capable of maintaining stability during higher temperature insulator deposition.  This investigation identifies the dimensional targets to fabricate successful bi-layer’s for use with sputtered insulators suitable for process optimization to facilitate evolving III-V applications.

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  • Nejim, Ahmed

    Silvaco Europe
    • Simulation of Leakage Induced Suppression of Bulk Dynamic RON in Power Switching GaN-on-Si HEMTs

      Martin Kuball, University of Bristol
      Michael Uren, University of Bristol
      Stefano Dalcanale, University of Bristol
      Feiyuan Yang, University of Bristol
      Ahmed Nejim, Silvaco Europe
      Stephen Wilson, Silvaco Europe

      Bulk induced dynamic RON in GaN-on-Si HEMTs is a serious performance limiting instability which remains a problem even in some commercially available power switching devices. Its origin is now reasonably well understood, however until now it has not been possible to simulate it using a realistic epitaxial stack. For the first time we successfully simulate the controlled suppression of bulk dynamic RON by adding a specific model for leakage along threading dislocations. This was undertaken using a commercially available standard TCAD simulator, allowing realistic device optimization in an advanced GaN HEMT design flow.

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  • Nevers, Corey

    Qorvo, Inc
    • eDataLyzer Application on Solving DS Yield Issue with Starburst Pattern

      Kim Kok Gan, Bistel America Inc
      Yiping Wang, Qorvo Inc.
      Robert Waco, Qorvo Inc.
      Matthew Johnson, Qorvo Inc.
      Pat Hamilton, Qorvo Inc.
      Jinhong Yang, Qorvo
      Dana Schwartz
      Corey Nevers, Qorvo, Inc
      Edward Elkan, Qorvo Inc.
      Kaushik Vaidyanathan, Qorvo Inc.

      A die sort (DS) yield loss forming a ‘starburst’ pattern in a wafermap was observed in a pHEMT technology manufactured by Qorvo. Typical data analysis performed by yield engineers was unable to correlate the failure root cause to a specific process step. To help drive to root cause, Bistel was consulted on the use of eDataLyzer (eDL) software.

      This paper will describe the ‘starburst’ DS yield loss pattern in details, followed by the application of Bistel’s eDL software combined with process tool Fault Detection and Correlation (FDC), and end with the validation of the failure mode.

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  • Nguyen, Vinh

    Qorvo Richardson
    • The Benefits of Cloud Analytics in Semiconductor – A Real-time Application Case Study

      Joe Lee, BISTel America
      Vinh Nguyen, Qorvo Richardson
      Eric McCormick, Qorvo, Inc.
      Gabe Villareal, BISTel America

      As we step into the era of Smart Manufacturing, a growing number of manufacturers across all industries are leveraging enabling technologies, such as Artificial intelligence (AI), Cloud, and Internet of Things (IOT), to help them improve productivity and profitability. Through an actual use case, this paper illustrates how one of these enabling technologies, Cloud computing, helps a semiconductor manufacturer overcome various challenges allowing them to be more productive and cost efficient.

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  • Nishimori, Masato

    Fujitsu Limited
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Nishimori, Masato

    Fujitsu Laboratories Ltd.
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Nomoto, Kazuki

    Cornell University
    • InAlN HEMT Epi and RF Devices on 8”-Si

      Huili Xing, Cornell University
      Ming Pan, Veeco Instruments
      Soo-Min Lee, Veeco Instruments
      Eric Tucker, Veeco Instruments
      Randhir Bubber, Veeco Instruments
      Ajit Paranjpe, Veeco Instruments
      Drew Hanser, Veeco Instruments, Inc.
      Kazuki Nomoto, Cornell University
      Lei Li, Cornell University
      Debdeep Jena, Cornell University

      In this paper, we report our work on epitaxial growth of InAlN HEMTs for RF device applications.  InAlN HEMTs were grown on 8” high resistivity silicon substrates. Various characterization techniques were used to analyze the quality of the epi wafers. An average sheet resistance (Rsh) of 206Ω/□, with a uniformity of 1.5% (1s/average), indicated a high quality and uniform 2DEG. Hall measurement showed a high sheet charge density of 2.27×1013cm−2 and a mobility of 1430cm2/(Vs). A pit free epi surface was obtained with optimized growth process of the active layers. T-gate RF devices fabricated on the InAlN epi wafers demonstrated an fT of 250GHz and an fMAX of 204 GHz, which are the record high values for GaN-based HEMTs on silicon.

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  • Odnoblyudov, Vlad

    QROMIS, USA
    • Integration of GaN Power ICs on 200 mm Engineered Substrates

      Stefaan Decoutere, Imec, Leuven, Belgium
      Xiangdong Li, imec
      Xiangdong Li, KU Leuven
      Karen Geens, imec, Leuven, Belgium
      Dirk Wellekens, imec
      Ming Zhao, imec
      Alessandro Magnani, imec
      Nooshin Amirifar, imec
      Benoit Bakeroot, imec, Leuven, Belgium and CMST, imec & Ghent University, Ghent, Belgium
      Shuzhen You, imec
      Dirk Fahle, AIXTRON SE
      Herwig Hahn, AIXTRON SE
      Michael Heuken, AIXTRON SE
      Vlad Odnoblyudov, QROMIS, USA
      Ozgur Aktas, QROMIS, USA
      Cem Basceri, QROMIS, USA
      Denis Marcon, imec
      Guido Groeseneken, KU Leuven
      Guido Groeseneken, imec

      GaN power ICs on engineered substrates of Qromis substrate technology (QST®) are promising for future power applications thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, high mechanical yield in combination with thick GaN buffer layers. In this work, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations show that the GaN buffer bear a breakdown voltage of > 650 V under the criterion of 10 μA/mm2 leakage current at 150 °C. The fabricated 36 mm power HEMTs with LGD of 16 µm show a high threshold voltage of 3.1 V and a low OFF-state drain leakage of <1 µA/mm until 650 V. The horizontal trench isolation breakdown voltage exceeds 850 V. The device dispersion is well controlled within 20% over full temperature and bias range. Finally, GaN power ICs on this platform are demonstrated.

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  • Ohki, Toshihiro

    Fujitsu Limited and Fujitsu Laboratories Ltd.
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Ohki, Toshihiro

    Fujitsu Laboratories Ltd.
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Okamoto, Naoya

    Fujitsu Limited and Fujitsu Laboratories Ltd.
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Okamoto, Naoya

    Fujitsu Laboratories Ltd.
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • OKAMOTO, Tomohiro

    CANON INC.
    • Study of new stepper solutions for various IoT devices

      Ken-Ichiro MORI, CANON INC.
      Noritoshi SAKAMOTO, CANON INC.
      Douglas SHELTON, CANON U.S.A. INC.
      Tomohiro OKAMOTO, CANON INC.
      Hiroyuki MIYAZAKI, CANON INC.

      To meet various process requirements from growing IoT devices, Canon has released FPA-3030iWa, FPA-3030i5+ and FPA-3030EX6 steppers based on the new FPA-3030 platform that is upgrade to the proven FPA-3000 stepper platform. In this paper, we will introduce FPA-3030iWa stepper solutions to support IoT device manufacturing and report evaluation data and advantages.

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  • Ostinelli, Olivier

    ETH-Zurich
    • Gate Recess Etch Sensitivity of Thick and Highly-Doped GaInAs Cap Layer in InP HEMT Fabrication

      Colombo Bolognesi, ETH-Zurich
      Daxin Han, ETH-Zürich
      Diego Calvo Ruiz, ETH-Zürich
      Tamara Saranovac, ETH-Zurich
      Olivier Ostinelli, ETH-Zurich

      The use of highly-doped thick cap layers is a common strategy to enhance the performance of GaInAs/AlInAs/InP High Electron Mobility Transistors (HEMTs) by reducing the Ohmic contact resistance (RC). However, because of the high doping level, cap layers become very sensitive to processing steps performed before and during gate recess etching. In this paper, the sensitivity of gate recess etching on a 20 nm highly-doped GaInAs cap layer (doped 7.3 × 1019 cm-3) is studied with respect to Ohmic contact type (annealed/non-annealed), chip size, gate finger length, and etchant choice. The use of very high cap doping levels exacerbates device and process scaling challenges. For example, the recess finger length dependence complicates multi-project wafer runs which would simultaneously include narrow finger HEMTs used in digital ICs and longer finger HEMTs used in microwave analog circuits.

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  • Ozaki, Shiro

    Fujitsu Limited and Fujitsu Laboratories Ltd.
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Ozaki, Shiro

    Fujitsu Limited
    • High-rate ICP Etching for GaN Through-substrate Via of GaN-on-GaN HEMTs

      Keiji Watanabe, Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoya Okamoto, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Laboratories Ltd.
      Atsushi Takahashi, Fujitsu Limited
      Yuichi Minoura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Yuichi Minoura, Fujitsu Laboratories Ltd.
      Yusuke Kumazaki, Fujitsu Limited
      Yusuke Kumazaki, Fujitsu Laboratories Ltd.
      Masato Nishimori, Fujitsu Limited
      Masato Nishimori, Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Shiro Ozaki, Fujitsu Limited
      Kozo Makiyama, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Kozo Makiyama, Fujitsu Limited
      Toshihiro Ohki, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Toshihiro Ohki, Fujitsu Laboratories Ltd.
      Norikazu Nakamura, Fujitsu Limited and Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Laboratories Ltd.
      Naoki Hara, Fujitsu Limited
      Keiji Watanabe, Fujitsu Limited

      In this study, we have developed a technique for forming GaN through-substrate vias (TSV) using inductively coupled plasma (ICP) dry etching with a gas mixture of Cl2/BCl3. A 91 μm-deep GaN via-hole having a diameter of 80 μm was successfully formed at a high etching rate of 1.5 μm/min and a high etching selectivity of 35. We discuss pillar formation, RIE lag, loading effects and etch uniformity in high-rate ICP etching, which are critical issues related to the yield of via-hole fabrication. Finally, we investigated the effect of GaN TSVs on heat dissipation by thermal simulation.

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  • Pal, Debdas

    MACOM
    • The Effect of Delay Between Pre-clean and Metal Deposition on the Forward Current Voltage Characteristics of Schottky Devices

      Eric Finchem, MACOM
      Debdas Pal, MACOM
      Lorain Ross, Skyworks Solutions, Inc.
      Sean Doonan, Skyworks Solutions, Inc.
      Edmund Burke, Skyworks Solutions, Inc.

      Schottky devices play an important role in modern electronics. The forward biased current-voltage characteristics of such devices are linear on a semi-logarithm scale at intermediate bias voltages. However, the curve deviates from linearity at higher voltage primarily due to series resistance. The applied forward voltage on the device is equal to the sum of the voltage drops across the (1) junction, (2) series resistance, (3) depletion layer and (4) any parasitic resistive layer between the Schottky metal and the semiconductor. Therefore, the interface between the metal and the semiconductor plays an important role in determining the critical parameters of Schottky devices. In this investigation a controlled delay was introduced between the pre-metal clean and Schottky metal deposition steps of the fabrication process to study the effects of naturally grown oxide on the forward characteristics of the Schottky devices.  The results of the investigation indicate such delays cause significant increases in series resistance and ideality factor, as well as a decrease in barrier height.

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  • Pan, Ming

    Veeco Instruments
    • InAlN HEMT Epi and RF Devices on 8”-Si

      Huili Xing, Cornell University
      Ming Pan, Veeco Instruments
      Soo-Min Lee, Veeco Instruments
      Eric Tucker, Veeco Instruments
      Randhir Bubber, Veeco Instruments
      Ajit Paranjpe, Veeco Instruments
      Drew Hanser, Veeco Instruments, Inc.
      Kazuki Nomoto, Cornell University
      Lei Li, Cornell University
      Debdeep Jena, Cornell University

      In this paper, we report our work on epitaxial growth of InAlN HEMTs for RF device applications.  InAlN HEMTs were grown on 8” high resistivity silicon substrates. Various characterization techniques were used to analyze the quality of the epi wafers. An average sheet resistance (Rsh) of 206Ω/□, with a uniformity of 1.5% (1s/average), indicated a high quality and uniform 2DEG. Hall measurement showed a high sheet charge density of 2.27×1013cm−2 and a mobility of 1430cm2/(Vs). A pit free epi surface was obtained with optimized growth process of the active layers. T-gate RF devices fabricated on the InAlN epi wafers demonstrated an fT of 250GHz and an fMAX of 204 GHz, which are the record high values for GaN-based HEMTs on silicon.

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  • Paranjpe, Ajit

    Veeco Instruments
    • InAlN HEMT Epi and RF Devices on 8”-Si

      Huili Xing, Cornell University
      Ming Pan, Veeco Instruments
      Soo-Min Lee, Veeco Instruments
      Eric Tucker, Veeco Instruments
      Randhir Bubber, Veeco Instruments
      Ajit Paranjpe, Veeco Instruments
      Drew Hanser, Veeco Instruments, Inc.
      Kazuki Nomoto, Cornell University
      Lei Li, Cornell University
      Debdeep Jena, Cornell University

      In this paper, we report our work on epitaxial growth of InAlN HEMTs for RF device applications.  InAlN HEMTs were grown on 8” high resistivity silicon substrates. Various characterization techniques were used to analyze the quality of the epi wafers. An average sheet resistance (Rsh) of 206Ω/□, with a uniformity of 1.5% (1s/average), indicated a high quality and uniform 2DEG. Hall measurement showed a high sheet charge density of 2.27×1013cm−2 and a mobility of 1430cm2/(Vs). A pit free epi surface was obtained with optimized growth process of the active layers. T-gate RF devices fabricated on the InAlN epi wafers demonstrated an fT of 250GHz and an fMAX of 204 GHz, which are the record high values for GaN-based HEMTs on silicon.

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  • Park, Myoungsoo

    Wavice Inc.
    • Qualification of Wavice Baseline GaN HEMT process with 0.4 um gate on 4” SiC wafers

      Hosang Kwon, Agency for Defense Development
      Sangmin Lee, Wavice Inc.
      Byoungchul Jun, Wavice Inc.
      Chulsoon choi, Wavice Inc.
      Hyeyoung Jung, Wavice Inc.
      Seokgyu Choi, Wavice Inc.
      Min Han, Wavice Inc.
      Ho Geun Lee, Wavice Inc.
      Myoungkeun Song, Wavice Inc.
      Sung Won Lee, Wavice Inc.
      Young Jae Kim, Wavice Inc.
      Jihun Kwon, Wavice Inc.
      Myoungsoo Park, Wavice Inc.
      Sewon Hwang, Wavice Inc.
      Hangyol Ji, Wavice Inc.

      The performance and reliability of AlGaN/AlN/GaN HEMT on 4 inch semi-insulating SiC substrate fabricated with baseline GaN HEMT process of Wavice Inc. have been reported. The baseline process of Wavice Inc. includes AlxGa1-xN/AlN/u-GaN/Fe-GaN epi structure with x=22%, Si+ ion implanted and recess etched ohmic, 0.4 um gate length, Ni based gamma Gate, electro plated void free source connected field plate (SCFP), 5 um thick electro plated interconnect metal, 85 um SiC substrate thickness after grinding, through SiC via directly to the source ohmic metal with sloped side wall, 7 um thick electro plated back side metal. To qualify the process technology, 3 non-consecutive lots were produced. DC/RF characterization and a list of reliability tests have been done on randomly selected devices.

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  • Parke, Justin

    Northrop Grumman Mission Systems
    • Productization of the Superlattice Castellated Field Effect Transistor

      Justin Parke, Northrop Grumman Mission Systems
      I. Wathuthanthri, Northrop Grumman (MS), Linthicum, MD
      Ken Nagamatsu, Northrop Grumman Mission Systems
      Josephine Chang, Northrop Grumman Mission Systems
      Georges Siddiqi, HRL Laboratories
      R. Lewis, Northrop Grumman (MS), Linthicum, MD
      Robert Howell, Northrop Grumman Mission Systems

      NGMS reports the maturation of a novel GaN based 3D transistor with state of the art RF switch performance, named the SLCFET (Super Lattice Castellated Field Effect Transistor), with an RF switch FOM greater than 1.8 THz. The configured process has undergone reliability qualification for production.

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  • Parz, Wolfgang

    MACOM Technology Solutions
    • Laser Diode Junction Temperature Assessment for Reliability Optimization

      Malcolm Green, MACOM Technology Solutions
      Charles Recchia, MACOM Technology Solutions
      Mark Bachman, MACOM Technology Solutions
      Lihua Hu, MACOM Technology Solutions
      Wolfgang Parz, MACOM Technology Solutions

      Determination of reliability performance over time requires an accurate understanding of device junction temperature, not only in customer use condition, but also during production test and burn-in. Through carefully designed and executed LIV (L=Light, I=current, V=Voltage) measurements and a modeling framework where optical power, thermal and electrical device parameters are interrelated, the laser diode junction temperature, as confirmed by wavelength shift measurements, is obtained via regression of a non-linear self-consistent equation.  Modeled parameters include both threshold current and slope efficiency junction linear temperature dependence coefficients/constants, as well as a thermal impedance factor.

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  • Peng, Yu-Ting

    University of Illinois, Urbana-Champaign
    • 850 nm GaAs P-i-N Photodiodes for 50 Gb/s Optical Links with Dark Current below 1 pA

      Dufei Wu, University of Illinois at Urbana Champaign
      Yu-Ting Peng, University of Illinois, Urbana-Champaign
      Milton Feng, University of Illinois, Urbana-Champaign

      Fabrication techniques and experimental data are presented for 850 nm GaAs P-i-N photodiodes designed for 50 Gb/s optical links. Optimizations in the device structure and the selective dry etching process reduce dark current below 1pA. Responsivity is shown to be comparable to commercial devices with similar dimensions. And microwave measurement shows a highest bandwidth of above 30 GHz, indicating potential for 60 Gb/s operation. Data rate testing is performed with a VCSEL up to 50 Gb/s, showing clear eye diagrams.

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  • Peng, Yu-Ting

    University of Illinois at Urbana Champaign
    • Wet-etching Process Problem Identification in Type-II InP DHBT for 5G Power Application

      Milton Feng, University of Illinois Urbana-Champaign
      Yu-Ting Peng, University of Illinois at Urbana Champaign
      Xin Yu, University of Illinois at Urbana-Champaign

      Wet-etching issues in type-II DHBT process fabricated by standard triple-mesa wet-etching have been identified and reported in this paper. For comparison, devices fabricated by hybrid-etching with incorporation of inductively-coupled-plasma (ICP) are also present. With better uniformity and yield, hybrid-etching process can potentially lead to a more reliable and reproducible process for 5G power amplifier application.

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  • Pool, Fred

    Qorvo
    • Effect of Process Variation on Pinch-Off Voltage of Depletion-Mode pHEMT

      Fred Pool, Qorvo
      Jinhong Yang, Qorvo
      Chang’e Weng, Qorvo
      Kaushik Vaidyanathan, Qorvo
      Moreen Minkoff, Qorvo
      Matthew Porter, Qorvo, Inc
      Michele Wilson, Qorvo
      Tertius River, Qorvo
      Mark Tesauro, Qorvo

      Pinch-off voltage is a key device characteristic of depletion-mode pseudomorphic high electron mobility transistors (pHEMT). Pinch-off voltage (Vp) shifts caused by manufacturing process variation were studied in this paper. Experimental results showed higher pinch-off voltage if the AlGaAs Schottky layer is oxidized or contaminated by metal. A significant increase in pinch-off voltage was observed when the Schottky layer was exposed to air for up to 2 hours after oxygen plasma treatment.  Investigation also revealed an increase in pinch-off voltage in relation to staging time and environment before gate contact metal deposition. In both cases, the effective thickness of the AlGaAs Schottky layer was reduced, and pinch-off voltage was increased. Models of metal cross-contamination and a “last wafer” effect in wet clean processing were also evaluated to address pinch-off voltage variation.

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  • Porter, Matthew

    Qorvo, Inc
    • Effect of Process Variation on Pinch-Off Voltage of Depletion-Mode pHEMT

      Fred Pool, Qorvo
      Jinhong Yang, Qorvo
      Chang’e Weng, Qorvo
      Kaushik Vaidyanathan, Qorvo
      Moreen Minkoff, Qorvo
      Matthew Porter, Qorvo, Inc
      Michele Wilson, Qorvo
      Tertius River, Qorvo
      Mark Tesauro, Qorvo

      Pinch-off voltage is a key device characteristic of depletion-mode pseudomorphic high electron mobility transistors (pHEMT). Pinch-off voltage (Vp) shifts caused by manufacturing process variation were studied in this paper. Experimental results showed higher pinch-off voltage if the AlGaAs Schottky layer is oxidized or contaminated by metal. A significant increase in pinch-off voltage was observed when the Schottky layer was exposed to air for up to 2 hours after oxygen plasma treatment.  Investigation also revealed an increase in pinch-off voltage in relation to staging time and environment before gate contact metal deposition. In both cases, the effective thickness of the AlGaAs Schottky layer was reduced, and pinch-off voltage was increased. Models of metal cross-contamination and a “last wafer” effect in wet clean processing were also evaluated to address pinch-off voltage variation.

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  • Prince, Kamau

    LayTec AG
    • Advanced semiconductor metrology and process control using UV-A/UV-B LEDs

      Kolja Haberland, LayTec AG
      Kamau Prince, LayTec AG
      Volker Blank, LayTec AG
      Johannes Zettler, LayTec AG

      Traditional in-situ reflectometry sensing at blue (405 nm), red (630 nm) and NIR (950 nm) wavelengths cannot resolve variations in InAlGaN surface roughness or layer thickness with the precision necessary for effective in situ process control. LayTec has developed in situ reflectance metrology at 280 nm to address this need.

      We report successful application of in situ UV reflect-ometry and curvature, distinguishing between various phases of strain relaxation and surface relaxation during non-pseudomorphic growth of Al0.5Ga0.5N on AlN/sapphire. Results were validated by XRD, TEM and AFM. Results illuminate the influence of reduced TDD on relaxation effects during growth of UVA and UVB LED structures.

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  • Raghunathan, Mukundkrishna

    KLA Corporation
    • Defect Inspection for Compound Semiconductor Wafers

      Mukundkrishna Raghunathan, KLA Corporation
      Varun Gupta, KLA-Tencor Limited
      Akash Nanda, KLA Corporation

      With expanding applications and growing performance requirements in Power, RF and Optoelectronics markets, leading device manufacturers are looking for new ways to characterize yield-limiting defects that will help them achieve faster development and ramp times, higher product yields and lower device costs. Full-surface, high sensitivity defect inspection and accurate process control feedback has enabled the industry to improve substrate quality as well as to optimize the yields on epitaxy growth processes.
           As device manufacturers continue to push the boundaries of process designs, the requirements for defect inspection and overall yield management become increasingly more stringent and critical. The Candela unified surface and photoluminescence (PL) defect inspection platform enables high sensitivity inspection and defect classification at production throughputs of a wide range of critical defects (e.g. micro scratches, stacking faults, basal plane dislocations) and effectively separates front-surface defects and buried defects on transparent SiC substrates and epitaxial material. In addition, automated defect classification capabilities reduce the time required to identify, source and correct various yield-limiting defects such as carrots, triangles, sub-micron pits and others.
           The process of growing III-V epitaxy has unique challenges. The large mismatch in the lattice constant and the thermal expansion coefficient between epitaxy layer and substrate causes high lattice stress which leads to cracking on and through the epitaxy layer, making parts of the wafer unsuitable for device production. This cracking can be minimized by using a suitable buffer layer and optimizing the epitaxy reactor conditions. Improper epitaxy reactor conditions may also cause other device reliability killer defects such as micropits, craters, epi droplets and/or bumps.
           This study discusses how multiple complementary techniques such as scatterometry, reflectometry, ellipsometry and photoluminescence could be used together for simultaneous detection and classification of multiple critical defects on compound semiconductor wafers. We demonstrate how feedback from defect inspection equipment can be used to screen incoming substrate wafers and to monitor and optimize the performance of CVD reactors during the epitaxy process.

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  • Rattray, Lori

    Kayaku Advanced Materials
    • Optimizing Bi-layer Lift-off Resist Processes for Insulator Films

      Lori Rattray, Kayaku Advanced Materials
      Robert Wadja, Kayaku Advanced Materials
      Dan Nawrocki, Kayaku Advanced Materials

      The bi-layer lift-off method has been used successfully to commercially fabricate many structures including source, drain ohmic contacts, gates and air bridges for use in Gallium Arsenide (GaAs), GaN, InP, MEMS and other semiconductor devices.  It is widely adopted for common pattern metallization processes.  The process utilizes LOR-PMGI (polydimethylglutarimide) plus an imaging resist to create a dual layer masking structure.  Uniquely, this structure can be customized because its composition and dimensions can be tailored for a given material-deposition-application system. This is enabling for use in select process applications.

      Deployment of VCSEL applications enabled by 5G latency advantages can benefit by using commercialized technology to comply industry development clockspeed.[1]  VCSEL devices can be broadly categorized in terms of deposition material thicknesses and structures based on power output.[2]  This study quantifies the most relevant bi-layer structural features for effective use with the reference metallization film, Aluminum.  It builds on these findings to explore the multivariate optimization required to successfully use bi-layer processing with common metal oxide insulators (SiO2 / Al2O3) in isotropically sputter deposited thicknesses of 100nm to 250nm.  A model is presented that characterizes the key variables.  Also, it introduces a new high temperature bi-layer process using a negative imaging resist capable of maintaining stability during higher temperature insulator deposition.  This investigation identifies the dimensional targets to fabricate successful bi-layer’s for use with sputtered insulators suitable for process optimization to facilitate evolving III-V applications.

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  • Recchia, Charles

    MACOM Technology Solutions
    • Laser Diode Junction Temperature Assessment for Reliability Optimization

      Malcolm Green, MACOM Technology Solutions
      Charles Recchia, MACOM Technology Solutions
      Mark Bachman, MACOM Technology Solutions
      Lihua Hu, MACOM Technology Solutions
      Wolfgang Parz, MACOM Technology Solutions

      Determination of reliability performance over time requires an accurate understanding of device junction temperature, not only in customer use condition, but also during production test and burn-in. Through carefully designed and executed LIV (L=Light, I=current, V=Voltage) measurements and a modeling framework where optical power, thermal and electrical device parameters are interrelated, the laser diode junction temperature, as confirmed by wavelength shift measurements, is obtained via regression of a non-linear self-consistent equation.  Modeled parameters include both threshold current and slope efficiency junction linear temperature dependence coefficients/constants, as well as a thermal impedance factor.

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  • Renz, Benjamin

    University of Warwick
    • Correlation study between molten KOH etching and laboratory X-ray Diffraction Imaging (X-ray topography) in n+ 4H-SiC wafers

      David Jacques, Bruker UK Ltd
      Vishal Shah, University of Warwick
      Richard Bytheway, Bruker UK Ltd
      Tamzin Lafford, Bruker UK Ltd
      Benjamin Renz, University of Warwick
      Peter Gammon, University of Warwick
      Paul Ryan, Bruker UK Ltd
      Hrishikesh Das, ON Semiconductor

      In order to meet the forecast growing demand of n+ SiC material, wafer suppliers will need to implement new metrology techniques to allow the detection of crystalline defects and ensure the quality of their materials. Incumbent techniques such as KOH etching have been used for many years but remain very costly as the wafers cannot be processed further. Alternative techniques such as X-ray Diffraction Imaging (X-ray Topography) can be used to detect crystalline defects non-destructively but studies have been limited to synchrotron radiation which cannot be used as an in-line characterization. In this paper, Bruker have used novel equipment (Sensus-CS) to study the correlation between laboratory X-ray Diffraction Imaging and KOH etching performed at the University of Warwick.

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  • Rieker, Jennifer

    EMD Performance Materials
    • Development and Testing of Sub 0.5-micron Features for Advanced Lift-Off Processes