12.13 Final.2025

Abstract
Dislocation of GaN epi has a strong correlation with reliability and electronic property of a GaN pHemt device. From technology development and field experience, dislocation under a device could cause possible reliability failure especially HTRB. In failure analysis for GaN dislocation, two beam condition of TEM is a common method, but the limitation of sample dimension and high cost are its disadvantages. In the literature, top-view observation by OM/SEM for etched epi by acid/base could be a reliable method for dislocation identification and density calculation[1][2][3]. By a series of experiments, we have developed an etching method by using molten KOH to obtain top-view SEM images of etched GaN epi and their correlation between defect density and reliability/electrical performance.

8A.3 Final.2025

Abstract
This study reports the melt growth of β-Ga2O3 single crystals using the Optical Floating Zone (OFZ) technique, and defect analysis in these wafers. X-ray diffraction (XRD) rocking curves show a full width at half maximum (FWHM) of 230 arcsec and the chemical mechanical polished surfaces exhibit a low surface roughness of 1.1 nm. Schottky barrier diodes (SBDs) were fabricated on these substrates and deep-level transient spectroscopy (DLTS) measurements were performed to investigate defects within the bandgap. DLTS analysis revealed a dominant single deep-level trap at 0.69 eV below the conduction band, attributed to Fe impurities from the source material used for melt-growth.

7A.2 Final.2025

Abstract
In this paper, we report 6-inch indium phosphide (InP) substrates with very low dislocation density produced using SEI’s Vertical Boat (VB) method. The growth conditions have been optimized to reduce crystal defects.

12.9 Final.2025

Abstract
The impact of chlorine-based etch conditions on etch profile and etched-surface quality was investigated. For this purpose, ALD HfSiOx/Ga2O3 trench-MOSCAPs were utilized as the test structure to understand the impact of etch conditions on sidewall quality (e.g. sidewall roughness and process-induced damage). UV-assisted capacitance-voltage measurements were employed to quantify the interface trap density.

7A.1 Final.2025

Abstract
In this work, we present the first demonstration of InP HBTs grown and fabricated on an engineered InPOSi substrate. Physical and electrical characterizations were performed to measure its crystal quality and device performance. We show that the performance of devices fabricated on an InPOSi substrate is close to devices fabricated on a native InP substrates making such a technology suitable for advanced RF applications. Fabricated devices show ft/fmax of ~140 GHz/70GHz with BVceo/BVcbo of 3.5 V/5.5 V at an ON current density of 8mA/μm2.

12.15 Final.2025

Abstract
Lithium Niobate (LN) substrates are prone to breakage through thermal shock. Thermal cycling is necessary for several processes in a wafer factory. To process LN wafers as quickly as possible without breaking these substrates, the mechanism for this breakage was investigated and found to be principally due to the cooling rate of the process.

7A.4 Final.2025

Abstract
The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Recently proton implantation has revealed its capability to block stacking fault expansion. We have evidenced through material characterization and electrical measurements of 1200 V PIN diodes that bipolar degradation can be mitigated above 1000 A/cm². A strong robustness has been evidenced through UV induced stacking faults. Electrical results are showing no visible bipolar degradation after a 600sec-2250 A/cm² stress test, while the reference material is showing a ~500mV drift at the device rated current of 10A.

10B.2 Final.2025

Abstract
This study presents a novel approach to device yield estimation based on the non-contact, corona-based QUAD(Quality, Uniformity, and Defects) technique for inline defect mapping in SiC epitaxial layers. The approach is applied to a merged PiN Schottky diode manufacturing process and is compared to final wafer level electrical data. A new analysis method for QUAD defect mapping is introduced, incorporating die yield bin maps based on indie depletion voltage values, allowing for a direct comparison with final electrical device performance. Micro-scale, QUAD and voltage data within each individual diode can gain further insight into the electrical nature of the defects causing the device failure. The results demonstrate a strong correlation between the inline QUAD bin map results and final device electrical properties, highlighting the potential of QUAD as a practical and powerful inline tool. This technique offers a complementary approach to UVPL defect imaging, identifying electrically active defects and enhancing estimations of the final production yield.

12.6 Final.2025

This paper presents Indium Tin Oxide (ITO) films developed using a pulsed DC off-axis sputtering chamber on 300mm substrates to obtain transparent-ohmic contact for pGaN. Film optoelectrical and microstructure properties were investigated per comparison for different deposition techniques such as single ITO target, alloy by co-deposition from two targets (In2O3 and SnO2) and for stacks including different interfacial layers, such as In-rich ITO and Ni. A ranking of the specific contact resistivity of all the films was determined after integration on Transmission Line Method (TLM) devices. A correlation of the specific contact resistivity with film first layer’s texture dependent on film process, thickness and material was observed.

3B.5 Final.2025

ABSTRACT
Planar vertical gallium nitride devices are capable of utilizing the beneficial material properties inherent to bulk GaN without the interference of surface leakage pathways or passivation failures inherent to lateral devices, however, the stability and long-term viability of implanted termination necessitates study. Here we show  stressing of 3.3kV vertical GaN diodes with nitrogen implanted termination at over 80% of the breakdown voltage and at up to 200°C for over 400 hours. Some diodes exhibit a burn-in effect with small changes to the breakdown voltage and leakage at breakdown while others exhibit robust and nearly invariant behavior to the limits of testing. Additionally, thermal stressing of a cohort of devices without bias shows an increased degradation of breakdown voltage above 300°C and differentiation of devices within the cohort beyond 350°C enabling further study of the degradation mechanisms.

4B.4 Final.2025

Abstract
Herein, we demonstrate top, bottom, and double-side thermal management strategies for gallium nitride (GaN) high electron mobility transistors (HEMTs). The cooling technologies investigated include GaN/SiC (reference), GaN/diamond (bottom-side), diamond/GaN/SiC (top-side), and diamond/GaN/diamond (double-side). We review processing methods to realize these device structures as well as the intricacies of the fabrication process. From DC output characteristics, the diamond/GaN/diamond HEMTs demonstrate over 0.6 A/mm at VGS = 2 V. From a thermal perspective, the double-side diamond cooling approach enabled operation at DC power densities of ~30 W/mm with a peak temperature rise of ~50 K at the drain-side edge of the gate electrode. Finally, we demonstrate our initial efforts towards diamond encasement of AlGaN/GaN epilayers to further reduce device-level thermal resistance.

7A.2 Final.2025

Abstract
In this paper, we report 6-inch indium phosphide (InP) substrates with very low dislocation density produced using SEI’s Vertical Boat (VB) method. The growth conditions have been optimized to reduce crystal defects.

7A.5 Final.2025

Abstract
This study presents a model developed to analyze crack formation during the heteroepitaxial growth of ultrawide-bandgap (UWBG) III-N semiconductor films on Si substrates. It addresses the challenges of growing thick (~>1.5 μm) crack-free AlN films, which is crucial for integrating Si with UWBG semiconductors. Utilizing Griffith theory of brittle fracture and Mathews-Blakeslee theory of dislocations, the model predicts crack formation in 500-nm AlN films driven by in-plane tensile stress during the cool-down process after deposition. To prevent this, a ductile epitaxial interlayer is introduced to modify the tensile strain in the AlN film. This approach successfully demonstrates the epitaxial growth of 1.5-μm single-crystalline, crack-free AlN film on a Si substrate.

12.9 Final.2025

Abstract
The impact of chlorine-based etch conditions on etch profile and etched-surface quality was investigated. For this purpose, ALD HfSiOx/Ga2O3 trench-MOSCAPs were utilized as the test structure to understand the impact of etch conditions on sidewall quality (e.g. sidewall roughness and process-induced damage). UV-assisted capacitance-voltage measurements were employed to quantify the interface trap density.

8A.3 Final.2025

Abstract
This study reports the melt growth of β-Ga2O3 single crystals using the Optical Floating Zone (OFZ) technique, and defect analysis in these wafers. X-ray diffraction (XRD) rocking curves show a full width at half maximum (FWHM) of 230 arcsec and the chemical mechanical polished surfaces exhibit a low surface roughness of 1.1 nm. Schottky barrier diodes (SBDs) were fabricated on these substrates and deep-level transient spectroscopy (DLTS) measurements were performed to investigate defects within the bandgap. DLTS analysis revealed a dominant single deep-level trap at 0.69 eV below the conduction band, attributed to Fe impurities from the source material used for melt-growth.

7A.4 Final.2025

Abstract
The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Recently proton implantation has revealed its capability to block stacking fault expansion. We have evidenced through material characterization and electrical measurements of 1200 V PIN diodes that bipolar degradation can be mitigated above 1000 A/cm². A strong robustness has been evidenced through UV induced stacking faults. Electrical results are showing no visible bipolar degradation after a 600sec-2250 A/cm² stress test, while the reference material is showing a ~500mV drift at the device rated current of 10A.

6A.1 Final.2025

Abstract
Traditional packaging technologies such as wire-bonding and lead-frames have served the compound semiconductor market well. As industry moves towards heterogeneous integration, there is an evolving need for advanced semiconductor packaging technologies for compound semiconductors. Extending these technologies towards the compound semiconductor market faces several challenges in terms of wafer sizes, packaging materials, thermal management, and reliability. This paper discusses advanced semiconductor packaging technologies, the heterogeneous integration roadmap, and the need for modelling technologies to support the packaging of compound semiconductors, their performance and reliability.

3A.5 Final.2025

Abstract
Lateral p-GaN gate-based power HEMTs are fabricated using a 9 μm thick GaN buffer on 200 mm GaN-on-QST® engineered substrates with a poly-AlN core, targeting 1200 V applications. The fabricated devices on engineered p-GaN gate on 9 μm thick GaN buffer show good ON/OFF state electrical characteristics and breakdown ~ 1800 V. The reliability of the fabricated p-GaN HEMTs were evaluated by a 1000-hour high temperature reverse bias (HTRB) stress test at 1200 V. No impact of HTRB stress was observed on electrical parameters and the devices yield a high pass rate.

7A.4 Final.2025

Abstract
The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Recently proton implantation has revealed its capability to block stacking fault expansion. We have evidenced through material characterization and electrical measurements of 1200 V PIN diodes that bipolar degradation can be mitigated above 1000 A/cm². A strong robustness has been evidenced through UV induced stacking faults. Electrical results are showing no visible bipolar degradation after a 600sec-2250 A/cm² stress test, while the reference material is showing a ~500mV drift at the device rated current of 10A.

2A.3 Final.2025

Abstract
We present the performances of our GaN MISHEMTs, using a thin buffer grown on SiC substrate, to pave the way for lateral GaN devices to exploit power applications in the voltage range up to 1700 V. Uni- and bi-directional MISHEMTs based on gate and source-connected field plate, with LGD = 21 μm achieve a breakdown voltage over 1800 V at a drain-source and gate currents less than 50 nA/mm. The on-resistance of the 1 mm gate width uni- and bidirectional devices were 9.5 Ω∙mm and 13.5 Ω∙mm, respectively, with a specific on-resistance of 2.7 mΩ∙cm2 and 4.4 mΩ∙cm2, respectively. The 1mm single MISHEMT results in a high Baliga figure of merit (BFOM) of 1.2 GW/cm2. A 147 mm gate width MISHEMT delivered 20 A pulse IDS current, at VGS =0 V and VDS = 1.5 V. Moreover, the MISHEMTs feature encouraging and superior stand in the breakdown voltage vs. on-resistance benchmark to commercial devices. We addressed the potential of the GaN-HEMTs to cover

12.17 Final.2025

Abstract
For high-performance GaN-based transistors, minimizing contact resistance is essential to reduce power losses and enhance switching efficiency. Achieving highly- doped contact areas in GaN is challenging due to its high binding energy and self-compensation effects. This study investigates the electrical activation of silicon-implanted GaN-on-sapphire structures using rapid thermal annealing (RTA) and optimized cap layers. Various cap materials, including sputtered and PECVD SiNx, Al2O3, and bilayer approaches, were evaluated for their ability to prevent GaN decomposition during high-temperature annealing. The best-performing cap consisted of a 10 nm thick CVD SiNx layer followed by 10 nm ALD Al2O3 layer, providing effective surface protection up to 1300 °C. Sheet resistance measurements indicate that higher annealing temperatures and optimized spike annealing conditions improve dopant activation, with the lowest sheet resistance of 188 Ω/□ achieved at 1400 °C using a two-spike process. These findings provide insights into optimizing thermal processes for high-performance GaN device fabrication.

6A.4 Final.2025

Abstract
This paper presents the thermal benefits of a heterogeneous integration (HI) technique for multi-chip assembly. The Metal Embedded Chip Assembly (MECA) process was used on a single thermal test chip to assess the thermal benefits of the embedded copper heat sink. Measurements were taken from the diodes on the thermal test chip as well as from the thermal images recorded with infrared camera. Simulation was done using COMSOL and are in unison agreement with the experimental results.

11A.1 Final.2025

Abstract – The utilization of electron beam lithography (EBL) as a wafer scale technique for the fabrication of compound semiconductor devices provides unique challenges in terms of both application and throughput. We report on wafer scale EBL in the context of fabricating edge emitting lasers on 150mm indium phosphide (InP) substrates. A hybrid electro-optical lithography process is used to pattern typical ridge waveguide (RWG) laser structures, while overcoming some of the practical challenges associated with fabricating these devices on large wafer platforms.

6B.2 Final.2025

A novel long wavelength 1550 nm VCSEL structure is introduced utilizing an InP-based substrate and bottom DBR mirror, a dielectric silicon/silicon dioxide top DBR mirror, and a tunable phase-matching layer fabricated from a piezo-electric/electro-optic material. By applying a voltage bias across this phase-matching layer, the layer’s optical thickness can be altered, thereby shifting the overlap of the electric-field standing-wave pattern with
the gain region. When process variation/nonuniformity negatively impact the device performance, mainly threshold current and threshold modal gain, tuning of the
phase matching layer can optimize the standing wave overlap with the gain region, minimizing threshold current and modal gain. This work presents the novel
epitaxial structure designed and explores the viability of various materials for application as the phase-matching layer via simulation results utilizing the transfer-matrix method.

7A.4 Final.2025

Abstract
The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Recently proton implantation has revealed its capability to block stacking fault expansion. We have evidenced through material characterization and electrical measurements of 1200 V PIN diodes that bipolar degradation can be mitigated above 1000 A/cm². A strong robustness has been evidenced through UV induced stacking faults. Electrical results are showing no visible bipolar degradation after a 600sec-2250 A/cm² stress test, while the reference material is showing a ~500mV drift at the device rated current of 10A.

2A.3 Final.2025

Abstract
We present the performances of our GaN MISHEMTs, using a thin buffer grown on SiC substrate, to pave the way for lateral GaN devices to exploit power applications in the voltage range up to 1700 V. Uni- and bi-directional MISHEMTs based on gate and source-connected field plate, with LGD = 21 μm achieve a breakdown voltage over 1800 V at a drain-source and gate currents less than 50 nA/mm. The on-resistance of the 1 mm gate width uni- and bidirectional devices were 9.5 Ω∙mm and 13.5 Ω∙mm, respectively, with a specific on-resistance of 2.7 mΩ∙cm2 and 4.4 mΩ∙cm2, respectively. The 1mm single MISHEMT results in a high Baliga figure of merit (BFOM) of 1.2 GW/cm2. A 147 mm gate width MISHEMT delivered 20 A pulse IDS current, at VGS =0 V and VDS = 1.5 V. Moreover, the MISHEMTs feature encouraging and superior stand in the breakdown voltage vs. on-resistance benchmark to commercial devices. We addressed the potential of the GaN-HEMTs to cover

3B.2 Final.2025

Abstract
A fabrication process for encapsulating T-gates with a robust SiN/SiO2 airbox has been developed at HRL, allowing for further passivation layers to be deposited, without creating additional parasitic capacitances that would degrade radio frequency (RF) performance of devices. This process has been demonstrated and validated on HRL’s T3 GaN devices, maintaining fT/fMAX after SiN and SiO2 coverage of the entire transistor. This robust inorganic airbox can be either used to enable wafer-level passivation of inorganic materials for complex BEOL fabrication and/or addition of moisture barrier layers to improve device reliability – all without altering device performance.

2A.3 Final.2025

Abstract
We present the performances of our GaN MISHEMTs, using a thin buffer grown on SiC substrate, to pave the way for lateral GaN devices to exploit power applications in the voltage range up to 1700 V. Uni- and bi-directional MISHEMTs based on gate and source-connected field plate, with LGD = 21 μm achieve a breakdown voltage over 1800 V at a drain-source and gate currents less than 50 nA/mm. The on-resistance of the 1 mm gate width uni- and bidirectional devices were 9.5 Ω∙mm and 13.5 Ω∙mm, respectively, with a specific on-resistance of 2.7 mΩ∙cm2 and 4.4 mΩ∙cm2, respectively. The 1mm single MISHEMT results in a high Baliga figure of merit (BFOM) of 1.2 GW/cm2. A 147 mm gate width MISHEMT delivered 20 A pulse IDS current, at VGS =0 V and VDS = 1.5 V. Moreover, the MISHEMTs feature encouraging and superior stand in the breakdown voltage vs. on-resistance benchmark to commercial devices. We addressed the potential of the GaN-HEMTs to cover

8A.2 Final.2025

Abstract
This work presents β-Ga2O3 trench Schottky barrier diodes (TSBDs) with double drift layer structures, achieving a 34% lower on-resistance compared to conventional single drift layer structures, without compromising the off-state performance. The TSBDs exhibit a breakdown voltage of ~2.4 kV, after which the devices were observed to crack along the [010] crystallographic direction in β-Ga2O3. The mechanisms behind breakdown-induced cracking were investigated including using nanoindentation, which revealed that the cracking is due to relatively weak chemical bonding along the [010] direction.

8A.4 Final.2025

Abstract
In this work, Gallium Oxide (β-Ga2O3) based trench Schottky barrier diodes (TSBDs) with field plate edge-termination are reported. The SiNx field plate edge-terminated TSBDs show an improvement in breakdown voltage up to 2.3 kV as compared to the unterminated structures of 1 kV. The electric field simulations show a reduction in peak electric field at the edge of the diodes when terminated with SiNx field plates. Reliability measurements were performed by reverse-bias step-stressing and observing the on-state performance post stressing. An increase in on-resistance for TSBDs with field plate edge termination up to 12% is observed when devices are stressed at 1 kV.

4A.3 Final.2025

Abstract
This paper presents dual-gate (2 × 0.5 μm) RF high electron mobility transistors (HEMTs) on P-GaN/AlGaN on Si substrate for next-generation airborne applications. The dual-gate architecture enhanced switching performance and reduced power loss, achieving a 77% reduction in off-state gate leakage current (0.3 mA/mm at VGS = -6V) and improving the ION/IOFF ratio by 1.9 orders of magnitude (5.45 × 10⁴) over single-gate devices. DC characterization revealed a current density (IDS) of 712 mA/mm, on-resistance (RON) of 3.12 Ω.mm, peak transconductance (GM) of 223 mS/mm, and pinch-off voltage (VP) of -2.4 V. S-parameter measurements showed a cut-off frequency (fT) of 7.12 GHz and a maximum oscillation frequency (fMAX) of 24.18 GHz. These results support the integration of the proposed RF devices with existing E-mode power devices on a single P-GaN/AlGaN HEMT on Si platform, paving the way for integrated transceiver modules.

7A.1 Final.2025

Abstract
In this work, we present the first demonstration of InP HBTs grown and fabricated on an engineered InPOSi substrate. Physical and electrical characterizations were performed to measure its crystal quality and device performance. We show that the performance of devices fabricated on an InPOSi substrate is close to devices fabricated on a native InP substrates making such a technology suitable for advanced RF applications. Fabricated devices show ft/fmax of ~140 GHz/70GHz with BVceo/BVcbo of 3.5 V/5.5 V at an ON current density of 8mA/μm2.

11B.4 Final.2025

Abstract
This study explores the effects of ion implantation and subsequent annealing on the resistivity of SiC. It investigates how implantation temperature, annealing temperature, and implantation beam current influence the recovery process of lattice damage and the resulting electrical properties. The results can be naturally interpreted in terms of cooperative molecular motions, which rule the structural rearrangements in locally disordered regions.
Our findings indicate that implantation at moderate temperatures, i.e. 500°C – 650°C, strikes an optimal balance between damage creation and recovery, leading to lower resistivity after high-temperature annealing (e.g., 1800°C). Higher implantation beam current reduces the duration of implantation, increasing post-implantation disorder, which in turn enhances the effectiveness of subsequent annealing. These results suggest that both the degree of initial disorder and the efficiency of recovery during annealing are critical factors in optimizing the electrical properties of ion-implanted semiconductors.

12.9 Final.2025

Abstract
The impact of chlorine-based etch conditions on etch profile and etched-surface quality was investigated. For this purpose, ALD HfSiOx/Ga2O3 trench-MOSCAPs were utilized as the test structure to understand the impact of etch conditions on sidewall quality (e.g. sidewall roughness and process-induced damage). UV-assisted capacitance-voltage measurements were employed to quantify the interface trap density.

3A.5 Final.2025

Abstract
Lateral p-GaN gate-based power HEMTs are fabricated using a 9 μm thick GaN buffer on 200 mm GaN-on-QST® engineered substrates with a poly-AlN core, targeting 1200 V applications. The fabricated devices on engineered p-GaN gate on 9 μm thick GaN buffer show good ON/OFF state electrical characteristics and breakdown ~ 1800 V. The reliability of the fabricated p-GaN HEMTs were evaluated by a 1000-hour high temperature reverse bias (HTRB) stress test at 1200 V. No impact of HTRB stress was observed on electrical parameters and the devices yield a high pass rate.

12.4 Final.2025

Abstract
Etch Pit Density (EPD) is a critical metric for assessing the quality of semiconductor wafers, providing insights into the density of dislocations and other crystal defects. The definition and measurement of robust and significant EPD evaluation parameters are essential for ensuring the performance, stability and cost efficiency of device manufacturing. In recent years the frontiers of low dislocation densities in VB/VGF grown GaAs and InP crystals have been pushed continuously. Traditional methods for EPD evaluation and assessment, while foundational, often fall short in addressing the complexities of modern semiconductor requirements. This paper will highlight the necessity of improving EPD counting and evaluation methods to meet the rigorous demands of contemporary semiconductor applications.

12.11 Final.2025

Abstract
In this paper, we focus on a simple hardware reconfiguration of CMP tools by deploying a slurry injection system (SIS) that modifies the slurry flow distribution, resulting in a more uniformly distributed thin layer of slurry on the polishing pad. The benefits of deploying the SIS on the CMP tools are clearly demonstrated: a 40-50% reduction in slurry flow rate — resulting in increasing throughput due to higher removal rate. A 2- 4% improvement in planarization was also obtained on patterned wafers polished with 5 kÅ of silicon dioxide (SiO2) deposited on top of a titanium/aluminum (Ti/Al) metal stack on a silicon substrate.

12.6 Final.2025

This paper presents Indium Tin Oxide (ITO) films developed using a pulsed DC off-axis sputtering chamber on 300mm substrates to obtain transparent-ohmic contact for pGaN. Film optoelectrical and microstructure properties were investigated per comparison for different deposition techniques such as single ITO target, alloy by co-deposition from two targets (In2O3 and SnO2) and for stacks including different interfacial layers, such as In-rich ITO and Ni. A ranking of the specific contact resistivity of all the films was determined after integration on Transmission Line Method (TLM) devices. A correlation of the specific contact resistivity with film first layer’s texture dependent on film process, thickness and material was observed.

3A.3 Final.2025

Abstract
In this study, we present vertical GaN based pn-diodes designed for high-voltage applications. These devices were initially grown and processed on 4-inch sapphire substrates and subsequently transferred to 4-inch tungsten substrates, enabling a fully vertical conduction path. Laser lift-off was employed to detach the GaN-membrane device structures from their original sapphire substrate. The diodes exhibit enhanced forward conduction following the transfer process, with the ON-state resistance decreasing from 1.52 ± 0.05 mΩcm2 to 1.15 ± 0.05 mΩcm2. During this time, the blocking strength remains largely unaffected, with its wafer level median value decreasing marginally from 1015 ± 47 V to 988 ± 57 V. The high device yields achieved through the membrane transfer procedure highlight the cost-competitiveness of this vertical GaN device technology for high-power applications, eliminating the need for expensive GaN substrates.

3A.3 Final.2025

Abstract
In this study, we present vertical GaN based pn-diodes designed for high-voltage applications. These devices were initially grown and processed on 4-inch sapphire substrates and subsequently transferred to 4-inch tungsten substrates, enabling a fully vertical conduction path. Laser lift-off was employed to detach the GaN-membrane device structures from their original sapphire substrate. The diodes exhibit enhanced forward conduction following the transfer process, with the ON-state resistance decreasing from 1.52 ± 0.05 mΩcm2 to 1.15 ± 0.05 mΩcm2. During this time, the blocking strength remains largely unaffected, with its wafer level median value decreasing marginally from 1015 ± 47 V to 988 ± 57 V. The high device yields achieved through the membrane transfer procedure highlight the cost-competitiveness of this vertical GaN device technology for high-power applications, eliminating the need for expensive GaN substrates.

10A.3 Final.2025

Abstract
VCSEL layer structures are among the most complicated ones in compound semiconductor device production. Re-establishing growth conditions for a new epi campaign after chamber maintenance can be challenging and time consuming. This work is about how to tackle this challenge by applying in-situ optical metrology during growth and processing of GaAs-based VCSEL devices as well as post-growth ex-situ wafer mapping. We demonstrate how to efficiently combine in-situ and ex-situ white light reflectance (WLR) measurements and modelling in order to increase the target wavelength accuracy.
Fitting the in-situ reflectance transient or the ex-situ WLR is used to generate a target reflectance trace for the subsequent plasma etching of the VCSEL mesa enabling automated end pointing.

11B.2 Final.2025

Abstract
Design of experiments (DOE) were performed to optimize resistance uniformity for TaN thin film resistors (TFR) across the Ta target’s life cycle. Fine-tuned photo-lithography recipes with exposure dose compensation (DC) minimized resistance variation introduced during the resistor layer’s (RL) photolithography and deposition processes. Experimental studies revealed how critical dimensions (CD) are influenced by the photoresist’s chemical amplification, substrate’s thermal history during post-exposure bake (PEB), and the coupling time (CT) between process-sensitive steps. The implementation of additional process controls within the RL fabrication process enhanced process capability (Cpk), tightened statistical process control (SPC) of TaN-related electrical parameters, and improved probe yield.

6A.2 Final.2025

Abstract
We demonstrate the heterogeneous integration of SWIR large-area InGaAs photodetectors and pixelated photodetector arrays on 300 mm CMOS-compatible Si (100) substrates through direct heteroepitaxy. The devices exhibit low dark current, high responsivity, low capacitance, and high quantum efficiency at shortwave infrared wavelengths.

2A.2 Final.2025

Abstract
In this study, vertical GaN trench MOSFETs were fabricated utilizing a novel gate dielectric composed of hafnium oxide (HfO₂) layered with aluminum oxide (Al₂O₃) to enhance device performance compared to those employing Al₂O₃ alone. The transistors incorporating the HfO₂ / Al₂O₃ layered gate dielectric exhibited up to three times increase in forward current, five times enhancement in gate breakdown voltage and significantly reduced threshold voltage shift induced by gate forward voltage stress, relative to devices with an Al₂O₃-only gate dielectric. Furthermore, the improved gate structure resulted in higher channel mobility (~11.1 cm²/Vs) and a reduced ON-state resistance (3.1 ± 0.6 mΩ·cm²).

3A.3 Final.2025

Abstract
In this study, we present vertical GaN based pn-diodes designed for high-voltage applications. These devices were initially grown and processed on 4-inch sapphire substrates and subsequently transferred to 4-inch tungsten substrates, enabling a fully vertical conduction path. Laser lift-off was employed to detach the GaN-membrane device structures from their original sapphire substrate. The diodes exhibit enhanced forward conduction following the transfer process, with the ON-state resistance decreasing from 1.52 ± 0.05 mΩcm2 to 1.15 ± 0.05 mΩcm2. During this time, the blocking strength remains largely unaffected, with its wafer level median value decreasing marginally from 1015 ± 47 V to 988 ± 57 V. The high device yields achieved through the membrane transfer procedure highlight the cost-competitiveness of this vertical GaN device technology for high-power applications, eliminating the need for expensive GaN substrates.

12.5 Final.2025

In this study, the reduction of contact resistance (Rc) in RF GaN HEMTs with an 8 nm Al₀.₃₆Ga₀.₆₄N barrier layer was investigated using two approaches: Si implantation and recess etching. Employing the Si implantation method with an optimized dopant activation procedure reduced Rc by 70% down to approximately 0.17 Ω·mm. In comparison, a reference alloyed Ti/Al/Ni/Au ohmic contact scheme without implantation achieved an Rc of ~0.60 Ω·mm. For the same epitaxial layer design, utilizing the recess etching technique reduced Rc by 50% down to 0.25 Ω·mm.

2A.2 Final.2025

Abstract
In this study, vertical GaN trench MOSFETs were fabricated utilizing a novel gate dielectric composed of hafnium oxide (HfO₂) layered with aluminum oxide (Al₂O₃) to enhance device performance compared to those employing Al₂O₃ alone. The transistors incorporating the HfO₂ / Al₂O₃ layered gate dielectric exhibited up to three times increase in forward current, five times enhancement in gate breakdown voltage and significantly reduced threshold voltage shift induced by gate forward voltage stress, relative to devices with an Al₂O₃-only gate dielectric. Furthermore, the improved gate structure resulted in higher channel mobility (~11.1 cm²/Vs) and a reduced ON-state resistance (3.1 ± 0.6 mΩ·cm²).

11B.2 Final.2025

Abstract
Design of experiments (DOE) were performed to optimize resistance uniformity for TaN thin film resistors (TFR) across the Ta target’s life cycle. Fine-tuned photo-lithography recipes with exposure dose compensation (DC) minimized resistance variation introduced during the resistor layer’s (RL) photolithography and deposition processes. Experimental studies revealed how critical dimensions (CD) are influenced by the photoresist’s chemical amplification, substrate’s thermal history during post-exposure bake (PEB), and the coupling time (CT) between process-sensitive steps. The implementation of additional process controls within the RL fabrication process enhanced process capability (Cpk), tightened statistical process control (SPC) of TaN-related electrical parameters, and improved probe yield.

12.9 Final.2025

Abstract
The impact of chlorine-based etch conditions on etch profile and etched-surface quality was investigated. For this purpose, ALD HfSiOx/Ga2O3 trench-MOSCAPs were utilized as the test structure to understand the impact of etch conditions on sidewall quality (e.g. sidewall roughness and process-induced damage). UV-assisted capacitance-voltage measurements were employed to quantify the interface trap density.

12.11 Final.2025

Abstract
In this paper, we focus on a simple hardware reconfiguration of CMP tools by deploying a slurry injection system (SIS) that modifies the slurry flow distribution, resulting in a more uniformly distributed thin layer of slurry on the polishing pad. The benefits of deploying the SIS on the CMP tools are clearly demonstrated: a 40-50% reduction in slurry flow rate — resulting in increasing throughput due to higher removal rate. A 2- 4% improvement in planarization was also obtained on patterned wafers polished with 5 kÅ of silicon dioxide (SiO2) deposited on top of a titanium/aluminum (Ti/Al) metal stack on a silicon substrate.

11B.4 Final.2025

Abstract
This study explores the effects of ion implantation and subsequent annealing on the resistivity of SiC. It investigates how implantation temperature, annealing temperature, and implantation beam current influence the recovery process of lattice damage and the resulting electrical properties. The results can be naturally interpreted in terms of cooperative molecular motions, which rule the structural rearrangements in locally disordered regions.
Our findings indicate that implantation at moderate temperatures, i.e. 500°C – 650°C, strikes an optimal balance between damage creation and recovery, leading to lower resistivity after high-temperature annealing (e.g., 1800°C). Higher implantation beam current reduces the duration of implantation, increasing post-implantation disorder, which in turn enhances the effectiveness of subsequent annealing. These results suggest that both the degree of initial disorder and the efficiency of recovery during annealing are critical factors in optimizing the electrical properties of ion-implanted semiconductors.

11A.2 Final.2025

Abstract
Coherent pluggable optics at 800 Gb/s and beyond are set to play a dominant role in optical networks over the next decade.
Infinera’s pluggable solutions are based on a monolithically integrated InP-based photonic integrated circuit (PIC), combining devices and functions required for a coherent optical transceiver. We will discuss the architecture and performance of several generations of InP-based PICs. Increased complexity in chip functionality has resulted in a need for increased fabrication complexity from III-V epitaxy, through wafer fab, die fab, and test. Through continuous learning and improvement, Infinera has fine-tuned the essential elements to successfully manufacture high-performance InP-based PICs. We will discuss manufacturing capability along with relevant yield and production metrics highlighting the manufacturability and scalability of this platform for pluggable components.
Recent industry trends have opened new and exciting markets where InP PICs offer benefits unmatched by any other technology. To meet these even higher volume manufacturing demands Infinera is investing in improved process technology and higher production capacity. We will discuss key challenges associated with this transition, and the outlook for further adoption of PIC technology.

3B.2 Final.2025

Abstract
A fabrication process for encapsulating T-gates with a robust SiN/SiO2 airbox has been developed at HRL, allowing for further passivation layers to be deposited, without creating additional parasitic capacitances that would degrade radio frequency (RF) performance of devices. This process has been demonstrated and validated on HRL’s T3 GaN devices, maintaining fT/fMAX after SiN and SiO2 coverage of the entire transistor. This robust inorganic airbox can be either used to enable wafer-level passivation of inorganic materials for complex BEOL fabrication and/or addition of moisture barrier layers to improve device reliability – all without altering device performance.

11B.1 Final.2025

Abstract
Silicon carbide (SiC) is a wide bandgap semiconductor material used to manufacture high-voltage and high-temperature operating devices. As SiC technology continues to advance, the density of devices across a wafer increases as transistors become smaller. On commonly used 6-inch SiC wafers, the wafers are subject to wafer bowing due to the physical hardness of the material. Conventional photolithography can lead to resolution inconsistencies across the wafer and significantly reduce yield. Cross-wafer yield is a challenge that can be addressed with e-beam lithography. E-beam direct-write lithography demonstrates superior fidelity of nanoscale features due to its great depth of focus over challenging topography on 6-inch and greater diameter SiC wafers.

12.19 Final.2025

Abstract
ITO layers were sputter-deposited onto commercially available vertical p/p+ diamond structures consisting of 5 μm thick p-type (1.2 × 1016 cm-3) drift layers deposited by Chemical Vapor Deposition on 250 μm thick heavily B-doped (3 × 1020 cm-3) single crystal substrates. The ITO is found to form a type II band alignment allowing Ohmic contact to the p-type diamond and creating a vertical n-p heterojunction. The maximum reverse breakdown of heterojunction rectifiers was ~1.1 kV, with an on-resistance (RON) of 13 mΩ•cm2, leading to a power figure-of-merit of 99.3 MW/cm2. The on-voltage was 1.4 V, diode ideality factor 1.22, with a reverse recovery time of 9.5 ns for 100 μm diameter rectifiers. The on/off ratios when switching from -5 V forward to 100 V reverse were in the range of 1011 to 1012. This is a simple approach to realizing high performance vertical diamond-based rectifiers for power switching applications.

12.6 Final.2025

This paper presents Indium Tin Oxide (ITO) films developed using a pulsed DC off-axis sputtering chamber on 300mm substrates to obtain transparent-ohmic contact for pGaN. Film optoelectrical and microstructure properties were investigated per comparison for different deposition techniques such as single ITO target, alloy by co-deposition from two targets (In2O3 and SnO2) and for stacks including different interfacial layers, such as In-rich ITO and Ni. A ranking of the specific contact resistivity of all the films was determined after integration on Transmission Line Method (TLM) devices. A correlation of the specific contact resistivity with film first layer’s texture dependent on film process, thickness and material was observed.

2B.1 Final.2025

Abstract
InGaN laser diodes are critical for rapidly growing technologies such as AR/VR, quantum, sensing, materials processing, biomedical, and solid-state lighting. This talk will focus on the development of epitaxial transfer and wafer-level facet formation processes that are enabling a new class of high performance InGaN laser diodes to support these new technologies. The advantages of these processes, such as better thermal management, improved device performance, wafer level manufacturing, and the ability to generate novel, integrated device architectures will be discussed. We will also present updates on the performance of high efficiency laser diodes spanning violet to green wavelengths and DFB laser architectures that enable power scaling while maintaining narrow linewidth.

2B.3 Final.2025

Abstract
This report investigates 940 nm vertical-cavity surface-emitting lasers (VCSELs) with three junctions (3J). The study focuses on the impact of oxide layers on the electrical and optical performance of these devices under various pulse conditions. Heat accumulation is a significant challenge in VCSELs, and shorter pulse durations reduce heat generation, improving thermal performance and minimizing lateral carrier diffusion in multi-junction structures. The results indicate that incorporating multiple oxide layers enhances carrier confinement, enabling output power exceeding 120 watts with 1.6-nanosecond pulses. However, using a single oxide layer decreases resistance and improves thermal dissipation, while maintaining output power above 100 watts. Spectral measurements revealed a red shift of less than 0.8 nm, corresponding to temperature variations of less than 12°C at 40A current injection. These findings provide valuable insights into the benefits and limitations of multi-junction VCSELs for next-generation sensing applications.

11B.2 Final.2025

Abstract
Design of experiments (DOE) were performed to optimize resistance uniformity for TaN thin film resistors (TFR) across the Ta target’s life cycle. Fine-tuned photo-lithography recipes with exposure dose compensation (DC) minimized resistance variation introduced during the resistor layer’s (RL) photolithography and deposition processes. Experimental studies revealed how critical dimensions (CD) are influenced by the photoresist’s chemical amplification, substrate’s thermal history during post-exposure bake (PEB), and the coupling time (CT) between process-sensitive steps. The implementation of additional process controls within the RL fabrication process enhanced process capability (Cpk), tightened statistical process control (SPC) of TaN-related electrical parameters, and improved probe yield.

3B.2 Final.2025

Abstract
A fabrication process for encapsulating T-gates with a robust SiN/SiO2 airbox has been developed at HRL, allowing for further passivation layers to be deposited, without creating additional parasitic capacitances that would degrade radio frequency (RF) performance of devices. This process has been demonstrated and validated on HRL’s T3 GaN devices, maintaining fT/fMAX after SiN and SiO2 coverage of the entire transistor. This robust inorganic airbox can be either used to enable wafer-level passivation of inorganic materials for complex BEOL fabrication and/or addition of moisture barrier layers to improve device reliability – all without altering device performance.

8A.2 Final.2025

Abstract
This work presents β-Ga2O3 trench Schottky barrier diodes (TSBDs) with double drift layer structures, achieving a 34% lower on-resistance compared to conventional single drift layer structures, without compromising the off-state performance. The TSBDs exhibit a breakdown voltage of ~2.4 kV, after which the devices were observed to crack along the [010] crystallographic direction in β-Ga2O3. The mechanisms behind breakdown-induced cracking were investigated including using nanoindentation, which revealed that the cracking is due to relatively weak chemical bonding along the [010] direction.

8A.3 Final.2025

Abstract
This study reports the melt growth of β-Ga2O3 single crystals using the Optical Floating Zone (OFZ) technique, and defect analysis in these wafers. X-ray diffraction (XRD) rocking curves show a full width at half maximum (FWHM) of 230 arcsec and the chemical mechanical polished surfaces exhibit a low surface roughness of 1.1 nm. Schottky barrier diodes (SBDs) were fabricated on these substrates and deep-level transient spectroscopy (DLTS) measurements were performed to investigate defects within the bandgap. DLTS analysis revealed a dominant single deep-level trap at 0.69 eV below the conduction band, attributed to Fe impurities from the source material used for melt-growth.

8A.4 Final.2025

Abstract
In this work, Gallium Oxide (β-Ga2O3) based trench Schottky barrier diodes (TSBDs) with field plate edge-termination are reported. The SiNx field plate edge-terminated TSBDs show an improvement in breakdown voltage up to 2.3 kV as compared to the unterminated structures of 1 kV. The electric field simulations show a reduction in peak electric field at the edge of the diodes when terminated with SiNx field plates. Reliability measurements were performed by reverse-bias step-stressing and observing the on-state performance post stressing. An increase in on-resistance for TSBDs with field plate edge termination up to 12% is observed when devices are stressed at 1 kV.

6B.4 Final.2025

ABSTRACT
In this work, we report the development of a high-precision fabrication process for microcavity VCSELs operating at cryogenic temperatures with oxide-aperture sizes below 3 μm. To address the critical challenge of controlling oxide-aperture size during wet oxidation, a novel hybrid etch mask combining SiNx and PR was introduced, enabling vertical mesa sidewall profiles with improved reliability and process uniformity. This approach enhances the accuracy of oxide formation, crucial for scaling down VCSEL apertures while maintaining thermal and optical performance. The fabricated Cryo-VCSEL with 1.7 m aperture demonstrates exceptional output power of 3.93 mW and modulation bandwidth exceeding 50 GHz at 2.9 K, with successful PAM-4 data transmission at 112 Gbps. The process yields minimal aperture variation (~ 0.5 μm IQR) across samples, ensuring suitability for parameter extraction and VCSEL array integration. These advancements establish a scalable fabrication platform for high-speed, cryogenic VCSELs, supporting future optical interconnects in quantum computing systems.

11B.4 Final.2025

Abstract
This study explores the effects of ion implantation and subsequent annealing on the resistivity of SiC. It investigates how implantation temperature, annealing temperature, and implantation beam current influence the recovery process of lattice damage and the resulting electrical properties. The results can be naturally interpreted in terms of cooperative molecular motions, which rule the structural rearrangements in locally disordered regions.
Our findings indicate that implantation at moderate temperatures, i.e. 500°C – 650°C, strikes an optimal balance between damage creation and recovery, leading to lower resistivity after high-temperature annealing (e.g., 1800°C). Higher implantation beam current reduces the duration of implantation, increasing post-implantation disorder, which in turn enhances the effectiveness of subsequent annealing. These results suggest that both the degree of initial disorder and the efficiency of recovery during annealing are critical factors in optimizing the electrical properties of ion-implanted semiconductors.

11B.1 Final.2025

Abstract
Silicon carbide (SiC) is a wide bandgap semiconductor material used to manufacture high-voltage and high-temperature operating devices. As SiC technology continues to advance, the density of devices across a wafer increases as transistors become smaller. On commonly used 6-inch SiC wafers, the wafers are subject to wafer bowing due to the physical hardness of the material. Conventional photolithography can lead to resolution inconsistencies across the wafer and significantly reduce yield. Cross-wafer yield is a challenge that can be addressed with e-beam lithography. E-beam direct-write lithography demonstrates superior fidelity of nanoscale features due to its great depth of focus over challenging topography on 6-inch and greater diameter SiC wafers.

12.18 Final.2025

Abstract
This material presents the technology development on 0.25um GaN High Electron Mobility Transistor (HEMT) on Silicon in WAVETEK Microelectronics. Epitaxy, process, BVD and RF characteristics are included in this material. The first process flow is designed for averaged power ≤ 20W and operation voltage@28V diverse power amplifier (PA) applications, e.g. massive MIMO basestation PA or phase array radar. DC performance of 4x100um device showed breakdown voltage > 200V. And RF results show fT, fmax (Vd=28V) = 28, 95 GHz, respectively. MSG/MAG= 23 dB @Vd= 28V and frequency= 3.5GHz. With optimized epitaxy structure and process, current collapse has been improved to 11.3%. Based on continuous wave (CW) load-pull measurement with harmonic tuning, (Vd=28V, Jc=20mA/mm, @3.5GHz), PAE@P3dB can achieve 70%, Gain= 19dB and Pout@P3dB can reach 32 dBm. For the other application of Vd=10V, e.g. WiFi Router PA and direct to cell PA, the 0.4mm HEMT device can achieve 2.1W. Adjacent Channel Leakage Ratio (ACLR) has been measured. The 4x100um HEMT results of raw ACPR (without DPD) are -39.3dBc/-38.6dBc. The overall performance is promising for 0.25um GaN on Silicon technology. The overall performance is promising for 0.25um GaN on Silicon technology.

12.18 Final.2025

Abstract
This material presents the technology development on 0.25um GaN High Electron Mobility Transistor (HEMT) on Silicon in WAVETEK Microelectronics. Epitaxy, process, BVD and RF characteristics are included in this material. The first process flow is designed for averaged power ≤ 20W and operation voltage@28V diverse power amplifier (PA) applications, e.g. massive MIMO basestation PA or phase array radar. DC performance of 4x100um device showed breakdown voltage > 200V. And RF results show fT, fmax (Vd=28V) = 28, 95 GHz, respectively. MSG/MAG= 23 dB @Vd= 28V and frequency= 3.5GHz. With optimized epitaxy structure and process, current collapse has been improved to 11.3%. Based on continuous wave (CW) load-pull measurement with harmonic tuning, (Vd=28V, Jc=20mA/mm, @3.5GHz), PAE@P3dB can achieve 70%, Gain= 19dB and Pout@P3dB can reach 32 dBm. For the other application of Vd=10V, e.g. WiFi Router PA and direct to cell PA, the 0.4mm HEMT device can achieve 2.1W. Adjacent Channel Leakage Ratio (ACLR) has been measured. The 4x100um HEMT results of raw ACPR (without DPD) are -39.3dBc/-38.6dBc. The overall performance is promising for 0.25um GaN on Silicon technology. The overall performance is promising for 0.25um GaN on Silicon technology.

12.13 Final.2025

Abstract
Dislocation of GaN epi has a strong correlation with reliability and electronic property of a GaN pHemt device. From technology development and field experience, dislocation under a device could cause possible reliability failure especially HTRB. In failure analysis for GaN dislocation, two beam condition of TEM is a common method, but the limitation of sample dimension and high cost are its disadvantages. In the literature, top-view observation by OM/SEM for etched epi by acid/base could be a reliable method for dislocation identification and density calculation[1][2][3]. By a series of experiments, we have developed an etching method by using molten KOH to obtain top-view SEM images of etched GaN epi and their correlation between defect density and reliability/electrical performance.

11B.1 Final.2025

Abstract
Silicon carbide (SiC) is a wide bandgap semiconductor material used to manufacture high-voltage and high-temperature operating devices. As SiC technology continues to advance, the density of devices across a wafer increases as transistors become smaller. On commonly used 6-inch SiC wafers, the wafers are subject to wafer bowing due to the physical hardness of the material. Conventional photolithography can lead to resolution inconsistencies across the wafer and significantly reduce yield. Cross-wafer yield is a challenge that can be addressed with e-beam lithography. E-beam direct-write lithography demonstrates superior fidelity of nanoscale features due to its great depth of focus over challenging topography on 6-inch and greater diameter SiC wafers.

2B.3 Final.2025

Abstract
This report investigates 940 nm vertical-cavity surface-emitting lasers (VCSELs) with three junctions (3J). The study focuses on the impact of oxide layers on the electrical and optical performance of these devices under various pulse conditions. Heat accumulation is a significant challenge in VCSELs, and shorter pulse durations reduce heat generation, improving thermal performance and minimizing lateral carrier diffusion in multi-junction structures. The results indicate that incorporating multiple oxide layers enhances carrier confinement, enabling output power exceeding 120 watts with 1.6-nanosecond pulses. However, using a single oxide layer decreases resistance and improves thermal dissipation, while maintaining output power above 100 watts. Spectral measurements revealed a red shift of less than 0.8 nm, corresponding to temperature variations of less than 12°C at 40A current injection. These findings provide valuable insights into the benefits and limitations of multi-junction VCSELs for next-generation sensing applications.

3A.4 Final.2025

Abstract
In this study we demonstrate that enhancement-mode behavior (Vₜₕ > 0) is achievable for β-Ga2O3 FinFET using a Fin width 𝑾𝑭𝑰𝑵≤0.5 μm and doping concentration 𝑵𝒅≤1×10¹⁶ cm⁻3. Breakdown voltage and output/transfer characteristics are calculated by using Drift-Diffusion methodology calibrated by experiments. We found that the metal work function (∅𝒎𝒔), dielectric constant (κ), and unintentional negative interface charge density (-Qf) at the β-Ga2O3/dielectric interface significantly impact Vₜₕ, with a high ∅𝒎𝒔 being necessary for enhancement mode operation. To achieve 5kV breakdown, a 𝑾𝑭𝑰𝑵 of 200 nm requires a fin thickness (𝑻𝑭𝑰𝑵) of 0.8 μm, a 𝑾𝑭𝑰𝑵 of 400 nm requires 𝑻𝑭𝑰𝑵> 1.2 μm, and a 𝑾𝑭𝑰𝑵 > 600 nm requires 𝑻𝑭𝑰𝑵 > 2 μm. From 𝑾𝑭𝑰𝑵 of 200 nm to 400 nm, DIBL (drain induced barrier lowering, i.e. Vₜₕ /Vds) increases by 300%, while from 400 to 600 nm, it rises by only 100%. -Qf increases breakdown voltage. Finally, β-Ga2O3 fin structures were fabricated to optimize etch profile.

4A.4 Final.2025

Abstract
E-mode p-GaN -gate RF HEMT with engineered Mg doping profile was developed and demonstrated for high power amplifier application. Through the design of a low-temperature MOCVD Mg doping profile and a reduction in Mg doping concentration, the diffusion of Mg into AlGaN is minimized compared to traditionally high Mg-doping grown p-GaN. This design enhances the gate modulation capability of p-GaN for RF applications, resulting in a higher gm peak. In addition, the Poole–Frenkel (PF) tunneling induced flicker noise was also suppressed at high input power swing due to low inactivated Mg induced traps. With the engineered Mg-doping profile design, a 61.4 % PAE was achieved together with an output power density close to 1 W/mm at VDS of 10 V which exhibit a highly potential for satellite direct-to-cell and FR3 mobile phone single voltage supply PA applications.

12.18 Final.2025

Abstract
This material presents the technology development on 0.25um GaN High Electron Mobility Transistor (HEMT) on Silicon in WAVETEK Microelectronics. Epitaxy, process, BVD and RF characteristics are included in this material. The first process flow is designed for averaged power ≤ 20W and operation voltage@28V diverse power amplifier (PA) applications, e.g. massive MIMO basestation PA or phase array radar. DC performance of 4x100um device showed breakdown voltage > 200V. And RF results show fT, fmax (Vd=28V) = 28, 95 GHz, respectively. MSG/MAG= 23 dB @Vd= 28V and frequency= 3.5GHz. With optimized epitaxy structure and process, current collapse has been improved to 11.3%. Based on continuous wave (CW) load-pull measurement with harmonic tuning, (Vd=28V, Jc=20mA/mm, @3.5GHz), PAE@P3dB can achieve 70%, Gain= 19dB and Pout@P3dB can reach 32 dBm. For the other application of Vd=10V, e.g. WiFi Router PA and direct to cell PA, the 0.4mm HEMT device can achieve 2.1W. Adjacent Channel Leakage Ratio (ACLR) has been measured. The 4x100um HEMT results of raw ACPR (without DPD) are -39.3dBc/-38.6dBc. The overall performance is promising for 0.25um GaN on Silicon technology. The overall performance is promising for 0.25um GaN on Silicon technology.

4A.4 Final.2025

Abstract
E-mode p-GaN -gate RF HEMT with engineered Mg doping profile was developed and demonstrated for high power amplifier application. Through the design of a low-temperature MOCVD Mg doping profile and a reduction in Mg doping concentration, the diffusion of Mg into AlGaN is minimized compared to traditionally high Mg-doping grown p-GaN. This design enhances the gate modulation capability of p-GaN for RF applications, resulting in a higher gm peak. In addition, the Poole–Frenkel (PF) tunneling induced flicker noise was also suppressed at high input power swing due to low inactivated Mg induced traps. With the engineered Mg-doping profile design, a 61.4 % PAE was achieved together with an output power density close to 1 W/mm at VDS of 10 V which exhibit a highly potential for satellite direct-to-cell and FR3 mobile phone single voltage supply PA applications.

12.13 Final.2025

Abstract
Dislocation of GaN epi has a strong correlation with reliability and electronic property of a GaN pHemt device. From technology development and field experience, dislocation under a device could cause possible reliability failure especially HTRB. In failure analysis for GaN dislocation, two beam condition of TEM is a common method, but the limitation of sample dimension and high cost are its disadvantages. In the literature, top-view observation by OM/SEM for etched epi by acid/base could be a reliable method for dislocation identification and density calculation[1][2][3]. By a series of experiments, we have developed an etching method by using molten KOH to obtain top-view SEM images of etched GaN epi and their correlation between defect density and reliability/electrical performance.

3A.5 Final.2025

Abstract
Lateral p-GaN gate-based power HEMTs are fabricated using a 9 μm thick GaN buffer on 200 mm GaN-on-QST® engineered substrates with a poly-AlN core, targeting 1200 V applications. The fabricated devices on engineered p-GaN gate on 9 μm thick GaN buffer show good ON/OFF state electrical characteristics and breakdown ~ 1800 V. The reliability of the fabricated p-GaN HEMTs were evaluated by a 1000-hour high temperature reverse bias (HTRB) stress test at 1200 V. No impact of HTRB stress was observed on electrical parameters and the devices yield a high pass rate.

11A.3 Final.2025

Abstract
Cost efficiency for data centers is providing an opportunity for quantum dot laser technology to move from a niche photonic process to a widely-adopted technology. This in turn drives the need for high-volume manufacturing methodologies in the production of QD epitaxial wafers. At the same time, integration of QDLs with Si photonics is an emerging focus. Epitaxy foundries such as IQE are drawing on their history of high-volume wafer manufacture to meet and manage the complexity associated with scaling QD epitaxy combined with end user device and integration needs. IQE is also able to leverage its capabilities to support next generation and emerging end user applications.

10B.3 Final.2025

Abstract
Silicon Carbide (SiC) power MOSFET performance depends on many key process and material properties. The drift layer active carrier concentration and thickness are important factors for defining device properties. Drift layer carrier concentration can be monitored easily by capacitance-voltage (CV) measurements. The leakage current (Ileak), breakdown voltage (VBD) and on-state resistivity (RON-sp) are all highly affected by control of the active carrier concentration profile and are monitorable by current-voltage (IV) measurements. Inadequate quality of the 4H-SiC epitaxial processes can degrade device performance and induce failure of the power MOSFET. In this paper, a high repeatability mercury probe is used to monitor these crucial electrical parameters and allows for a rapid response in improving and predicting final device behavior.

7A.1 Final.2025

Abstract
In this work, we present the first demonstration of InP HBTs grown and fabricated on an engineered InPOSi substrate. Physical and electrical characterizations were performed to measure its crystal quality and device performance. We show that the performance of devices fabricated on an InPOSi substrate is close to devices fabricated on a native InP substrates making such a technology suitable for advanced RF applications. Fabricated devices show ft/fmax of ~140 GHz/70GHz with BVceo/BVcbo of 3.5 V/5.5 V at an ON current density of 8mA/μm2.

2A.1 Final.2025

Abstract
Electron mobility as high as 300 cm2/Vs and resistivity as low as 26 Ω·cm were demonstrated in Si-doped AlN by applying point and extended defect management to suppress compensation. Using this doping capability, AlN Schottky barrier diodes were designed and fabricated. The diodes are capable of passing kA/cm2 in the forward bias while simultaneously blocking voltages in the kV range. These results demonstrate the feasibility of AlN as a platform for next-generation power electronics.

11A.4 Final.2025

Abstract
In this work, the development of solar-blind ultraviolet detectors based on the AlGaN materials system is discussed. This development includes design, growth, characterization, fabrication, and packaging of devices in a vertically integrated environment. The advantage of keeping all major steps needed to realize the devices in-house is discussed with focus on process control and holistic device manufacturing. Finally, device properties including sensitivity and efficiency are presented and an outlook on future developments is given.

3B.3 Final.2025

Abstract
This paper presents a novel cavity coplanar waveguide (CCPW) structure based on GaN-on-SiC technology for high-power microwave applications. The CCPW structure was fabricated using an emerging monolithic microwave integrated circuit (MMIC)-compatible localised electrodeposition metal additive micro-manufacturing (μAM) process, achieving an air-bridge height of 50 μm. Electromagnetic (EM) simulations revealed that introducing a cavity above the CPW improves impedance matching at mm-wave frequencies while providing a robust ground-return path. S-parameter measurements show that the CCPW provides a 6.5 dB improvement in reflection coefficient at 110 GHz compared to a standard coplanar waveguide (CPW) structure. Furthermore, both simulations and measurements indicate a broadband reflection coefficient trough suggesting the potential for broadband impedance matching in MMIC applications. To further analyse RF parasitics, a high-frequency equivalent circuit model was developed, demonstrating significant performance improvements of the CCPW compared to a printed air-bridge.

4A.3 Final.2025

Abstract
This paper presents dual-gate (2 × 0.5 μm) RF high electron mobility transistors (HEMTs) on P-GaN/AlGaN on Si substrate for next-generation airborne applications. The dual-gate architecture enhanced switching performance and reduced power loss, achieving a 77% reduction in off-state gate leakage current (0.3 mA/mm at VGS = -6V) and improving the ION/IOFF ratio by 1.9 orders of magnitude (5.45 × 10⁴) over single-gate devices. DC characterization revealed a current density (IDS) of 712 mA/mm, on-resistance (RON) of 3.12 Ω.mm, peak transconductance (GM) of 223 mS/mm, and pinch-off voltage (VP) of -2.4 V. S-parameter measurements showed a cut-off frequency (fT) of 7.12 GHz and a maximum oscillation frequency (fMAX) of 24.18 GHz. These results support the integration of the proposed RF devices with existing E-mode power devices on a single P-GaN/AlGaN HEMT on Si platform, paving the way for integrated transceiver modules.

2A.4 Final.2025

Abstract

Vertical GaN MOSFETs are a promising technology for next generation efficient power systems. Here we investigate the effect of operating temperature on the on-state performance of quasi-vertical GaN MOSFETs, fabricated on SiC substrates. The threshold voltage, transconductance and on-resistance were extracted from measured characteristics across a range of temperatures. Shifts in both threshold voltage and transconductance are attributed to temperature dependent trapping-detrapping at the MOS interface. These are discussed in relation to series resistance contributions in the channel, drift layer and access resistances at the source and drain contacts.

3A.4 Final.2025

Abstract
In this study we demonstrate that enhancement-mode behavior (Vₜₕ > 0) is achievable for β-Ga2O3 FinFET using a Fin width 𝑾𝑭𝑰𝑵≤0.5 μm and doping concentration 𝑵𝒅≤1×10¹⁶ cm⁻3. Breakdown voltage and output/transfer characteristics are calculated by using Drift-Diffusion methodology calibrated by experiments. We found that the metal work function (∅𝒎𝒔), dielectric constant (κ), and unintentional negative interface charge density (-Qf) at the β-Ga2O3/dielectric interface significantly impact Vₜₕ, with a high ∅𝒎𝒔 being necessary for enhancement mode operation. To achieve 5kV breakdown, a 𝑾𝑭𝑰𝑵 of 200 nm requires a fin thickness (𝑻𝑭𝑰𝑵) of 0.8 μm, a 𝑾𝑭𝑰𝑵 of 400 nm requires 𝑻𝑭𝑰𝑵> 1.2 μm, and a 𝑾𝑭𝑰𝑵 > 600 nm requires 𝑻𝑭𝑰𝑵 > 2 μm. From 𝑾𝑭𝑰𝑵 of 200 nm to 400 nm, DIBL (drain induced barrier lowering, i.e. Vₜₕ /Vds) increases by 300%, while from 400 to 600 nm, it rises by only 100%. -Qf increases breakdown voltage. Finally, β-Ga2O3 fin structures were fabricated to optimize etch profile.

6A.4 Final.2025

Abstract
This paper presents the thermal benefits of a heterogeneous integration (HI) technique for multi-chip assembly. The Metal Embedded Chip Assembly (MECA) process was used on a single thermal test chip to assess the thermal benefits of the embedded copper heat sink. Measurements were taken from the diodes on the thermal test chip as well as from the thermal images recorded with infrared camera. Simulation was done using COMSOL and are in unison agreement with the experimental results.

3B.3 Final.2025

Abstract
This paper presents a novel cavity coplanar waveguide (CCPW) structure based on GaN-on-SiC technology for high-power microwave applications. The CCPW structure was fabricated using an emerging monolithic microwave integrated circuit (MMIC)-compatible localised electrodeposition metal additive micro-manufacturing (μAM) process, achieving an air-bridge height of 50 μm. Electromagnetic (EM) simulations revealed that introducing a cavity above the CPW improves impedance matching at mm-wave frequencies while providing a robust ground-return path. S-parameter measurements show that the CCPW provides a 6.5 dB improvement in reflection coefficient at 110 GHz compared to a standard coplanar waveguide (CPW) structure. Furthermore, both simulations and measurements indicate a broadband reflection coefficient trough suggesting the potential for broadband impedance matching in MMIC applications. To further analyse RF parasitics, a high-frequency equivalent circuit model was developed, demonstrating significant performance improvements of the CCPW compared to a printed air-bridge.

12.6 Final.2025

This paper presents Indium Tin Oxide (ITO) films developed using a pulsed DC off-axis sputtering chamber on 300mm substrates to obtain transparent-ohmic contact for pGaN. Film optoelectrical and microstructure properties were investigated per comparison for different deposition techniques such as single ITO target, alloy by co-deposition from two targets (In2O3 and SnO2) and for stacks including different interfacial layers, such as In-rich ITO and Ni. A ranking of the specific contact resistivity of all the films was determined after integration on Transmission Line Method (TLM) devices. A correlation of the specific contact resistivity with film first layer’s texture dependent on film process, thickness and material was observed.

4A.2 Final.2025

Abstract
We conducted DC and small-signal RF characterization on AlGaN/GaN high-electron-mobility transistors (HEMTs) over a range of temperatures to examine temperature-dependent variations in key device performance metrics including transconductance (gm), extrinsic cutoff frequency (fT), maximum gain frequency (fmax), unilateral power gain (UPG), and maximum stable gain (MSG). Our findings indicate that device parameters decline with increasing temperature at a distinct rate. Specifically, a 100°C rise results in fT and fmax dropping by about 8 GHz and 17 GHz, respectively, while MSG decreases by approximately 1 dB. These changes are inherent to the device physics and are not influenced by its geometry or operational mode.

12.10 Final.2025

Abstract
At ATL, innovation drives the development of new technologies to meet customer needs, including in the semiconductor fabrication process. Shifts in processing can lead to issues like cross-contamination, impacting processes such as L-Band power transistor production. Residue left after photoresist strip processes caused concerns, affecting wafer quality and potentially leading to emitter-base shorts. Through a rigorous investigation and experimentation with different photoresist strip methods, a more effective approach using an alternate Asher tool was found. Implementing this new method significantly reduced residue, improving production yield and resolving process challenges in semiconductor manufacturing at ATL.

4B.4 Final.2025

Abstract
Herein, we demonstrate top, bottom, and double-side thermal management strategies for gallium nitride (GaN) high electron mobility transistors (HEMTs). The cooling technologies investigated include GaN/SiC (reference), GaN/diamond (bottom-side), diamond/GaN/SiC (top-side), and diamond/GaN/diamond (double-side). We review processing methods to realize these device structures as well as the intricacies of the fabrication process. From DC output characteristics, the diamond/GaN/diamond HEMTs demonstrate over 0.6 A/mm at VGS = 2 V. From a thermal perspective, the double-side diamond cooling approach enabled operation at DC power densities of ~30 W/mm with a peak temperature rise of ~50 K at the drain-side edge of the gate electrode. Finally, we demonstrate our initial efforts towards diamond encasement of AlGaN/GaN epilayers to further reduce device-level thermal resistance.

12.2 Final.2025

Abstract
RF-plasma assisted nitridation was used to transform (100) -Ga2O3 to (0001) wurtzite GaN and subsequently grow a 520 nm p-GaN cap layer over 5 intervals. The final step involved a 11.5 hour anneal at the growth temperature of 680 C to allow for equilibration inside the crystal body. The nitridated film was characterized via X-ray diffraction (XRD), which revealed peaks distinct from the (0001) family. Analysis of these distinct peaks revealed varying (𝒉𝟎𝒍) orientations. We theorize that the alternate orientations are forming to accommodate the growing GaN film, gradually shifting towards the ideal heteroepitaxy plane of (𝟐̅𝟎𝟏). XRD rocking curves of the (0002) GaN were used to analyze crystallinity as a function of thickness. Results showed a transformation at the 120 nm interval, from a single Gaussian-like peak to a broad-narrow dual peak configuration. The FWHM’s were extracted and plotted against a previous study, indicating narrower, improved peak of 20%.

12.3 Final.2025

Abstract
Silicon nitride shadowed selective area growth (SNS-SAG) for homoepitaxy of GaN via RF plasma-assisted molecular beam epitaxy (PAMBE) has been shown to avoid the defects that arise from conventional selective area processing methods such as inductively coupled plasma reactive ion etching (ICP-RIE) and ion implantation. This work investigates the extension of this method to improve the heteroepitaxy of GaN on β-Ga2O3 by modifying the makeup of the SNS-SAG mask. Gallium rich and nitrogen rich GaN films are grown with SNS-SAG masks on β-Ga2O3 substrates. While current device performance has yet to be optimized, the adapted SNS-SAG mask retains both function and structural integrity as shown by scanning electron microscopy (SEM).

2A.3 Final.2025

Abstract
We present the performances of our GaN MISHEMTs, using a thin buffer grown on SiC substrate, to pave the way for lateral GaN devices to exploit power applications in the voltage range up to 1700 V. Uni- and bi-directional MISHEMTs based on gate and source-connected field plate, with LGD = 21 μm achieve a breakdown voltage over 1800 V at a drain-source and gate currents less than 50 nA/mm. The on-resistance of the 1 mm gate width uni- and bidirectional devices were 9.5 Ω∙mm and 13.5 Ω∙mm, respectively, with a specific on-resistance of 2.7 mΩ∙cm2 and 4.4 mΩ∙cm2, respectively. The 1mm single MISHEMT results in a high Baliga figure of merit (BFOM) of 1.2 GW/cm2. A 147 mm gate width MISHEMT delivered 20 A pulse IDS current, at VGS =0 V and VDS = 1.5 V. Moreover, the MISHEMTs feature encouraging and superior stand in the breakdown voltage vs. on-resistance benchmark to commercial devices. We addressed the potential of the GaN-HEMTs to cover

4B.1 Final.2025

Abstract
TO packaging continues to replace air cavity ceramic
as a lower cost package for high power RF devices.
Advances in the plastic overmold materials and process
along with wire bonding have enabled its use with the
increasing power demands of GaN devices. This paper will
describe these advances and the interactions with GaN
devices that have led to a lower cost, high performing, and
reliable packaging solution.

2B.2 Final.2025

In this work, impurity-induced disordering by Zn diffusion is proposed as a method for lateral current confinement in InP-based quantum cascade lasers. This method improves current confinement for a shallow ridge-guide laser bar while preserving material for lateral thermal dissipation and avoiding an increase of optical loss. Using ZnAs2 solid source, the diffusion profiles and rates in an InGaAs/InAlAs superlattice is characterized. A diffusion coefficient of 7.35×10-12 cm2/s is extracted for a 550 ºC process. Zn-driven impurity-induced disordering of an InGaAs/InAlAs superlattice is experimentally demonstrated. Two-terminal electrical modeling is performed to verify improved confinement of the injected electrons. Furthermore, analysis of the optical mode is performed to determine the best mask and diffusion parameters. Optical modeling results indicate feasible diffusion profiles with a decrease in waveguide loss (from 13.041 cm-1 to 12.77 cm-1) and minimal change in gain overlap (51.15% to 51.13%). Finally, quantum cascade material is processed and electrically characterized with initial indications of a reduction of lateral current spreading by 61%.

6B.2 Final.2025

A novel long wavelength 1550 nm VCSEL structure is introduced utilizing an InP-based substrate and bottom DBR mirror, a dielectric silicon/silicon dioxide top DBR mirror, and a tunable phase-matching layer fabricated from a piezo-electric/electro-optic material. By applying a voltage bias across this phase-matching layer, the layer’s optical thickness can be altered, thereby shifting the overlap of the electric-field standing-wave pattern with
the gain region. When process variation/nonuniformity negatively impact the device performance, mainly threshold current and threshold modal gain, tuning of the
phase matching layer can optimize the standing wave overlap with the gain region, minimizing threshold current and modal gain. This work presents the novel
epitaxial structure designed and explores the viability of various materials for application as the phase-matching layer via simulation results utilizing the transfer-matrix method.

10A.4 Final.2025

2D-VCSEL arrays utilizing elliptical disorder-defined apertures for simultaneous single-mode, singlepolarization operation are demonstrated. Optical losses induced by the disordered region in the periphery of the VCSEL suppress the capability of higher-order modes from lasing, achieving single-fundamental mode
operation. Furthermore, introducing eccentricity to the aperture creates an asymmetric threshold gain, or dichroism, that selectively suppresses one of the two polarization states inherent to VCSELs, resulting in single-polarization operation. The work presented here discusses the design, fabrication, and characterization results of the 2D-VCSEL arrays. The arrays are characterized for optical output power, single-mode performance via optical spectra measurements, and single-polarization performance via polarization-resolved light-current-voltage (PR-LIV) curves.

12.12 Final.2025

Abstract
Scaling interconnects to increase device density is a critical bottleneck for a range of applications in the 3D and advanced packaging fields. Currently, interconnect density is limited by, among other things, the ability to produce reliable, low resistivity Cu vias at high aspect ratios (AR). While some progress has been made, single side deposition, used in blind vias, is limited to 8:1 or 10:1. This limit is enforced by the adhesion and/or nucleation layer required for successful Cu electrochemical deposition (ECD). Current techniques provide high quality layers, but those layers are applied in a non-conformal fashion, leading to device failure at high AR or in reentrant features. Atomic layer deposition (ALD) is a vapor-phase deposition technique that can produce low resistivity metal films conformally over any feature accessible by process gas. In this work, we demonstrate successful Cu seed application by depositing a low-resistivity Ru metal film on Si trenches and through glass vias (TGV). Successful conformal ECD has been demonstrated with 10-20 nm of Ru in blind silicon vias with AR from 4:1 to 25:1 and in TGV with AR from 6:1 to 30:1. Further tests are ongoing to measure via resistivity after Cu ECD and to explore higher AR vias, such as 50:1.

3A.3 Final.2025

Abstract
In this study, we present vertical GaN based pn-diodes designed for high-voltage applications. These devices were initially grown and processed on 4-inch sapphire substrates and subsequently transferred to 4-inch tungsten substrates, enabling a fully vertical conduction path. Laser lift-off was employed to detach the GaN-membrane device structures from their original sapphire substrate. The diodes exhibit enhanced forward conduction following the transfer process, with the ON-state resistance decreasing from 1.52 ± 0.05 mΩcm2 to 1.15 ± 0.05 mΩcm2. During this time, the blocking strength remains largely unaffected, with its wafer level median value decreasing marginally from 1015 ± 47 V to 988 ± 57 V. The high device yields achieved through the membrane transfer procedure highlight the cost-competitiveness of this vertical GaN device technology for high-power applications, eliminating the need for expensive GaN substrates.

10B.4 Final.2025

As frequencies increase, the use of smaller value metal-insulator-metal (MIM) capacitors increases. For small capacitors, errors due to the bias of the top plate can cause significant errors. This bias is not correctly monitored with resistance based dW (RLWB) monitors. We present a simple capacitive based technique that uses only two test patterns to determine the value of the capacitive linewidth bias (CLWB) that is more appropriate for use electromagnetic (EM) simulation.

11B.2 Final.2025

Abstract
Design of experiments (DOE) were performed to optimize resistance uniformity for TaN thin film resistors (TFR) across the Ta target’s life cycle. Fine-tuned photo-lithography recipes with exposure dose compensation (DC) minimized resistance variation introduced during the resistor layer’s (RL) photolithography and deposition processes. Experimental studies revealed how critical dimensions (CD) are influenced by the photoresist’s chemical amplification, substrate’s thermal history during post-exposure bake (PEB), and the coupling time (CT) between process-sensitive steps. The implementation of additional process controls within the RL fabrication process enhanced process capability (Cpk), tightened statistical process control (SPC) of TaN-related electrical parameters, and improved probe yield.

8A.3 Final.2025

Abstract
This study reports the melt growth of β-Ga2O3 single crystals using the Optical Floating Zone (OFZ) technique, and defect analysis in these wafers. X-ray diffraction (XRD) rocking curves show a full width at half maximum (FWHM) of 230 arcsec and the chemical mechanical polished surfaces exhibit a low surface roughness of 1.1 nm. Schottky barrier diodes (SBDs) were fabricated on these substrates and deep-level transient spectroscopy (DLTS) measurements were performed to investigate defects within the bandgap. DLTS analysis revealed a dominant single deep-level trap at 0.69 eV below the conduction band, attributed to Fe impurities from the source material used for melt-growth.

11A.2 Final.2025

Abstract
Coherent pluggable optics at 800 Gb/s and beyond are set to play a dominant role in optical networks over the next decade.
Infinera’s pluggable solutions are based on a monolithically integrated InP-based photonic integrated circuit (PIC), combining devices and functions required for a coherent optical transceiver. We will discuss the architecture and performance of several generations of InP-based PICs. Increased complexity in chip functionality has resulted in a need for increased fabrication complexity from III-V epitaxy, through wafer fab, die fab, and test. Through continuous learning and improvement, Infinera has fine-tuned the essential elements to successfully manufacture high-performance InP-based PICs. We will discuss manufacturing capability along with relevant yield and production metrics highlighting the manufacturability and scalability of this platform for pluggable components.
Recent industry trends have opened new and exciting markets where InP PICs offer benefits unmatched by any other technology. To meet these even higher volume manufacturing demands Infinera is investing in improved process technology and higher production capacity. We will discuss key challenges associated with this transition, and the outlook for further adoption of PIC technology.

3A.3 Final.2025

Abstract
In this study, we present vertical GaN based pn-diodes designed for high-voltage applications. These devices were initially grown and processed on 4-inch sapphire substrates and subsequently transferred to 4-inch tungsten substrates, enabling a fully vertical conduction path. Laser lift-off was employed to detach the GaN-membrane device structures from their original sapphire substrate. The diodes exhibit enhanced forward conduction following the transfer process, with the ON-state resistance decreasing from 1.52 ± 0.05 mΩcm2 to 1.15 ± 0.05 mΩcm2. During this time, the blocking strength remains largely unaffected, with its wafer level median value decreasing marginally from 1015 ± 47 V to 988 ± 57 V. The high device yields achieved through the membrane transfer procedure highlight the cost-competitiveness of this vertical GaN device technology for high-power applications, eliminating the need for expensive GaN substrates.

12.4 Final.2025

Abstract
Etch Pit Density (EPD) is a critical metric for assessing the quality of semiconductor wafers, providing insights into the density of dislocations and other crystal defects. The definition and measurement of robust and significant EPD evaluation parameters are essential for ensuring the performance, stability and cost efficiency of device manufacturing. In recent years the frontiers of low dislocation densities in VB/VGF grown GaAs and InP crystals have been pushed continuously. Traditional methods for EPD evaluation and assessment, while foundational, often fall short in addressing the complexities of modern semiconductor requirements. This paper will highlight the necessity of improving EPD counting and evaluation methods to meet the rigorous demands of contemporary semiconductor applications.

6A.4 Final.2025

Abstract
This paper presents the thermal benefits of a heterogeneous integration (HI) technique for multi-chip assembly. The Metal Embedded Chip Assembly (MECA) process was used on a single thermal test chip to assess the thermal benefits of the embedded copper heat sink. Measurements were taken from the diodes on the thermal test chip as well as from the thermal images recorded with infrared camera. Simulation was done using COMSOL and are in unison agreement with the experimental results.

12.6 Final.2025

This paper presents Indium Tin Oxide (ITO) films developed using a pulsed DC off-axis sputtering chamber on 300mm substrates to obtain transparent-ohmic contact for pGaN. Film optoelectrical and microstructure properties were investigated per comparison for different deposition techniques such as single ITO target, alloy by co-deposition from two targets (In2O3 and SnO2) and for stacks including different interfacial layers, such as In-rich ITO and Ni. A ranking of the specific contact resistivity of all the films was determined after integration on Transmission Line Method (TLM) devices. A correlation of the specific contact resistivity with film first layer’s texture dependent on film process, thickness and material was observed.

4B.2 Final.2025

Abstract
This paper discusses Qorvo’s recent release of Cu Pillar (CuP) interconnect technology with Ni barrier on high frequency Gallium Nitride (GaN) HEMTs fabricated on Silicon Carbide (SiC) 150 mm substrates. Ongoing multi-temperature High Temperature Storage (HTS) tests indicate > 2×106 h median lifetime for CuP joints at 85ºC. Different types of CuP Ni plating are being studied which display a difference in lifetimes. Results demonstrate the use of ENEPIG finish on the laminate substrates could further increase CuP solder-joint reliability, allowing their use at temperatures up to 125ºC.

6A.2 Final.2025

Abstract
We demonstrate the heterogeneous integration of SWIR large-area InGaAs photodetectors and pixelated photodetector arrays on 300 mm CMOS-compatible Si (100) substrates through direct heteroepitaxy. The devices exhibit low dark current, high responsivity, low capacitance, and high quantum efficiency at shortwave infrared wavelengths.

3B.3 Final.2025

Abstract
This paper presents a novel cavity coplanar waveguide (CCPW) structure based on GaN-on-SiC technology for high-power microwave applications. The CCPW structure was fabricated using an emerging monolithic microwave integrated circuit (MMIC)-compatible localised electrodeposition metal additive micro-manufacturing (μAM) process, achieving an air-bridge height of 50 μm. Electromagnetic (EM) simulations revealed that introducing a cavity above the CPW improves impedance matching at mm-wave frequencies while providing a robust ground-return path. S-parameter measurements show that the CCPW provides a 6.5 dB improvement in reflection coefficient at 110 GHz compared to a standard coplanar waveguide (CPW) structure. Furthermore, both simulations and measurements indicate a broadband reflection coefficient trough suggesting the potential for broadband impedance matching in MMIC applications. To further analyse RF parasitics, a high-frequency equivalent circuit model was developed, demonstrating significant performance improvements of the CCPW compared to a printed air-bridge.

4A.3 Final.2025

Abstract
This paper presents dual-gate (2 × 0.5 μm) RF high electron mobility transistors (HEMTs) on P-GaN/AlGaN on Si substrate for next-generation airborne applications. The dual-gate architecture enhanced switching performance and reduced power loss, achieving a 77% reduction in off-state gate leakage current (0.3 mA/mm at VGS = -6V) and improving the ION/IOFF ratio by 1.9 orders of magnitude (5.45 × 10⁴) over single-gate devices. DC characterization revealed a current density (IDS) of 712 mA/mm, on-resistance (RON) of 3.12 Ω.mm, peak transconductance (GM) of 223 mS/mm, and pinch-off voltage (VP) of -2.4 V. S-parameter measurements showed a cut-off frequency (fT) of 7.12 GHz and a maximum oscillation frequency (fMAX) of 24.18 GHz. These results support the integration of the proposed RF devices with existing E-mode power devices on a single P-GaN/AlGaN HEMT on Si platform, paving the way for integrated transceiver modules.

11B.2 Final.2025

Abstract
Design of experiments (DOE) were performed to optimize resistance uniformity for TaN thin film resistors (TFR) across the Ta target’s life cycle. Fine-tuned photo-lithography recipes with exposure dose compensation (DC) minimized resistance variation introduced during the resistor layer’s (RL) photolithography and deposition processes. Experimental studies revealed how critical dimensions (CD) are influenced by the photoresist’s chemical amplification, substrate’s thermal history during post-exposure bake (PEB), and the coupling time (CT) between process-sensitive steps. The implementation of additional process controls within the RL fabrication process enhanced process capability (Cpk), tightened statistical process control (SPC) of TaN-related electrical parameters, and improved probe yield.

12.4 Final.2025

Abstract
Etch Pit Density (EPD) is a critical metric for assessing the quality of semiconductor wafers, providing insights into the density of dislocations and other crystal defects. The definition and measurement of robust and significant EPD evaluation parameters are essential for ensuring the performance, stability and cost efficiency of device manufacturing. In recent years the frontiers of low dislocation densities in VB/VGF grown GaAs and InP crystals have been pushed continuously. Traditional methods for EPD evaluation and assessment, while foundational, often fall short in addressing the complexities of modern semiconductor requirements. This paper will highlight the necessity of improving EPD counting and evaluation methods to meet the rigorous demands of contemporary semiconductor applications.

3B.3 Final.2025

Abstract
This paper presents a novel cavity coplanar waveguide (CCPW) structure based on GaN-on-SiC technology for high-power microwave applications. The CCPW structure was fabricated using an emerging monolithic microwave integrated circuit (MMIC)-compatible localised electrodeposition metal additive micro-manufacturing (μAM) process, achieving an air-bridge height of 50 μm. Electromagnetic (EM) simulations revealed that introducing a cavity above the CPW improves impedance matching at mm-wave frequencies while providing a robust ground-return path. S-parameter measurements show that the CCPW provides a 6.5 dB improvement in reflection coefficient at 110 GHz compared to a standard coplanar waveguide (CPW) structure. Furthermore, both simulations and measurements indicate a broadband reflection coefficient trough suggesting the potential for broadband impedance matching in MMIC applications. To further analyse RF parasitics, a high-frequency equivalent circuit model was developed, demonstrating significant performance improvements of the CCPW compared to a printed air-bridge.

4A.3 Final.2025

Abstract
This paper presents dual-gate (2 × 0.5 μm) RF high electron mobility transistors (HEMTs) on P-GaN/AlGaN on Si substrate for next-generation airborne applications. The dual-gate architecture enhanced switching performance and reduced power loss, achieving a 77% reduction in off-state gate leakage current (0.3 mA/mm at VGS = -6V) and improving the ION/IOFF ratio by 1.9 orders of magnitude (5.45 × 10⁴) over single-gate devices. DC characterization revealed a current density (IDS) of 712 mA/mm, on-resistance (RON) of 3.12 Ω.mm, peak transconductance (GM) of 223 mS/mm, and pinch-off voltage (VP) of -2.4 V. S-parameter measurements showed a cut-off frequency (fT) of 7.12 GHz and a maximum oscillation frequency (fMAX) of 24.18 GHz. These results support the integration of the proposed RF devices with existing E-mode power devices on a single P-GaN/AlGaN HEMT on Si platform, paving the way for integrated transceiver modules.

2A.4 Final.2025

Abstract

Vertical GaN MOSFETs are a promising technology for next generation efficient power systems. Here we investigate the effect of operating temperature on the on-state performance of quasi-vertical GaN MOSFETs, fabricated on SiC substrates. The threshold voltage, transconductance and on-resistance were extracted from measured characteristics across a range of temperatures. Shifts in both threshold voltage and transconductance are attributed to temperature dependent trapping-detrapping at the MOS interface. These are discussed in relation to series resistance contributions in the channel, drift layer and access resistances at the source and drain contacts.

6B.2 Final.2025

A novel long wavelength 1550 nm VCSEL structure is introduced utilizing an InP-based substrate and bottom DBR mirror, a dielectric silicon/silicon dioxide top DBR mirror, and a tunable phase-matching layer fabricated from a piezo-electric/electro-optic material. By applying a voltage bias across this phase-matching layer, the layer’s optical thickness can be altered, thereby shifting the overlap of the electric-field standing-wave pattern with
the gain region. When process variation/nonuniformity negatively impact the device performance, mainly threshold current and threshold modal gain, tuning of the
phase matching layer can optimize the standing wave overlap with the gain region, minimizing threshold current and modal gain. This work presents the novel
epitaxial structure designed and explores the viability of various materials for application as the phase-matching layer via simulation results utilizing the transfer-matrix method.

10A.4 Final.2025

2D-VCSEL arrays utilizing elliptical disorder-defined apertures for simultaneous single-mode, singlepolarization operation are demonstrated. Optical losses induced by the disordered region in the periphery of the VCSEL suppress the capability of higher-order modes from lasing, achieving single-fundamental mode
operation. Furthermore, introducing eccentricity to the aperture creates an asymmetric threshold gain, or dichroism, that selectively suppresses one of the two polarization states inherent to VCSELs, resulting in single-polarization operation. The work presented here discusses the design, fabrication, and characterization results of the 2D-VCSEL arrays. The arrays are characterized for optical output power, single-mode performance via optical spectra measurements, and single-polarization performance via polarization-resolved light-current-voltage (PR-LIV) curves.

3A.4 Final.2025

Abstract
In this study we demonstrate that enhancement-mode behavior (Vₜₕ > 0) is achievable for β-Ga2O3 FinFET using a Fin width 𝑾𝑭𝑰𝑵≤0.5 μm and doping concentration 𝑵𝒅≤1×10¹⁶ cm⁻3. Breakdown voltage and output/transfer characteristics are calculated by using Drift-Diffusion methodology calibrated by experiments. We found that the metal work function (∅𝒎𝒔), dielectric constant (κ), and unintentional negative interface charge density (-Qf) at the β-Ga2O3/dielectric interface significantly impact Vₜₕ, with a high ∅𝒎𝒔 being necessary for enhancement mode operation. To achieve 5kV breakdown, a 𝑾𝑭𝑰𝑵 of 200 nm requires a fin thickness (𝑻𝑭𝑰𝑵) of 0.8 μm, a 𝑾𝑭𝑰𝑵 of 400 nm requires 𝑻𝑭𝑰𝑵> 1.2 μm, and a 𝑾𝑭𝑰𝑵 > 600 nm requires 𝑻𝑭𝑰𝑵 > 2 μm. From 𝑾𝑭𝑰𝑵 of 200 nm to 400 nm, DIBL (drain induced barrier lowering, i.e. Vₜₕ /Vds) increases by 300%, while from 400 to 600 nm, it rises by only 100%. -Qf increases breakdown voltage. Finally, β-Ga2O3 fin structures were fabricated to optimize etch profile.

11A.2 Final.2025

Abstract
Coherent pluggable optics at 800 Gb/s and beyond are set to play a dominant role in optical networks over the next decade.
Infinera’s pluggable solutions are based on a monolithically integrated InP-based photonic integrated circuit (PIC), combining devices and functions required for a coherent optical transceiver. We will discuss the architecture and performance of several generations of InP-based PICs. Increased complexity in chip functionality has resulted in a need for increased fabrication complexity from III-V epitaxy, through wafer fab, die fab, and test. Through continuous learning and improvement, Infinera has fine-tuned the essential elements to successfully manufacture high-performance InP-based PICs. We will discuss manufacturing capability along with relevant yield and production metrics highlighting the manufacturability and scalability of this platform for pluggable components.
Recent industry trends have opened new and exciting markets where InP PICs offer benefits unmatched by any other technology. To meet these even higher volume manufacturing demands Infinera is investing in improved process technology and higher production capacity. We will discuss key challenges associated with this transition, and the outlook for further adoption of PIC technology.

10B.2 Final.2025

Abstract
This study presents a novel approach to device yield estimation based on the non-contact, corona-based QUAD(Quality, Uniformity, and Defects) technique for inline defect mapping in SiC epitaxial layers. The approach is applied to a merged PiN Schottky diode manufacturing process and is compared to final wafer level electrical data. A new analysis method for QUAD defect mapping is introduced, incorporating die yield bin maps based on indie depletion voltage values, allowing for a direct comparison with final electrical device performance. Micro-scale, QUAD and voltage data within each individual diode can gain further insight into the electrical nature of the defects causing the device failure. The results demonstrate a strong correlation between the inline QUAD bin map results and final device electrical properties, highlighting the potential of QUAD as a practical and powerful inline tool. This technique offers a complementary approach to UVPL defect imaging, identifying electrically active defects and enhancing estimations of the final production yield.

8B.5 Final.2025

Abstract
NSTC updates as of March 7, 2025. The year 2024 was an inflection point for U.S. semiconductor R&D and innovation. From the signing of the National Semiconductor Technology Center1 (NSTC) consortium agreement in February to the establishment of foundational semiconductor research programs, national workforce development initiatives, and the announcement of state-of-the-art research facilities throughout the year, 2024 laid the groundwork for long-term success for U.S.-led semiconductor innovation. These milestones represent the beginning of a critical, sustained, and collaborative effort to drive technological advancement, build economic resilience, and strengthen national security in the United States.

6B.4 Final.2025

ABSTRACT
In this work, we report the development of a high-precision fabrication process for microcavity VCSELs operating at cryogenic temperatures with oxide-aperture sizes below 3 μm. To address the critical challenge of controlling oxide-aperture size during wet oxidation, a novel hybrid etch mask combining SiNx and PR was introduced, enabling vertical mesa sidewall profiles with improved reliability and process uniformity. This approach enhances the accuracy of oxide formation, crucial for scaling down VCSEL apertures while maintaining thermal and optical performance. The fabricated Cryo-VCSEL with 1.7 m aperture demonstrates exceptional output power of 3.93 mW and modulation bandwidth exceeding 50 GHz at 2.9 K, with successful PAM-4 data transmission at 112 Gbps. The process yields minimal aperture variation (~ 0.5 μm IQR) across samples, ensuring suitability for parameter extraction and VCSEL array integration. These advancements establish a scalable fabrication platform for high-speed, cryogenic VCSELs, supporting future optical interconnects in quantum computing systems.

11B.5 Final.2025

Abstract
In this work, the effects of emitter ledging on DC and RF performance in sub-micron InP DHBTs are investigated. We have demonstrated that incorporating a 160-nm emitter ledge leads to an over 100% increase in DC current gain (β), rising from 16 to 34. This gain increase is primarily due to the suppression of emitter peripheral surface recombination. However, increased emitter ledge also leads to a reduction in device high frequency fT and fMAX performance due to increase in device transit time and extrinsic resistance. Trade-off between enhanced beta gain and degraded RF bandwidth needs to be further studied on the emitter ledge length.

11B.1 Final.2025

Abstract
Silicon carbide (SiC) is a wide bandgap semiconductor material used to manufacture high-voltage and high-temperature operating devices. As SiC technology continues to advance, the density of devices across a wafer increases as transistors become smaller. On commonly used 6-inch SiC wafers, the wafers are subject to wafer bowing due to the physical hardness of the material. Conventional photolithography can lead to resolution inconsistencies across the wafer and significantly reduce yield. Cross-wafer yield is a challenge that can be addressed with e-beam lithography. E-beam direct-write lithography demonstrates superior fidelity of nanoscale features due to its great depth of focus over challenging topography on 6-inch and greater diameter SiC wafers.

6A.4 Final.2025

Abstract
This paper presents the thermal benefits of a heterogeneous integration (HI) technique for multi-chip assembly. The Metal Embedded Chip Assembly (MECA) process was used on a single thermal test chip to assess the thermal benefits of the embedded copper heat sink. Measurements were taken from the diodes on the thermal test chip as well as from the thermal images recorded with infrared camera. Simulation was done using COMSOL and are in unison agreement with the experimental results.

6A.3 Final.2025

Abstract
This paper presents Circuits Integrated Hellas’s (CIH) innovative use of III-V compound semiconductors with advanced 3D packaging. CIH introduces disruptive, high-performance solutions for satellite communication (SatCom) applications, leveraging System-in-Package (SiP) and Antenna-in-Package (AiP) methodologies. These approaches minimize the weight, volume, and cost of flat-panel phased array antennas, addressing a critical need in modern space communications

3A.4 Final.2025

Abstract
In this study we demonstrate that enhancement-mode behavior (Vₜₕ > 0) is achievable for β-Ga2O3 FinFET using a Fin width 𝑾𝑭𝑰𝑵≤0.5 μm and doping concentration 𝑵𝒅≤1×10¹⁶ cm⁻3. Breakdown voltage and output/transfer characteristics are calculated by using Drift-Diffusion methodology calibrated by experiments. We found that the metal work function (∅𝒎𝒔), dielectric constant (κ), and unintentional negative interface charge density (-Qf) at the β-Ga2O3/dielectric interface significantly impact Vₜₕ, with a high ∅𝒎𝒔 being necessary for enhancement mode operation. To achieve 5kV breakdown, a 𝑾𝑭𝑰𝑵 of 200 nm requires a fin thickness (𝑻𝑭𝑰𝑵) of 0.8 μm, a 𝑾𝑭𝑰𝑵 of 400 nm requires 𝑻𝑭𝑰𝑵> 1.2 μm, and a 𝑾𝑭𝑰𝑵 > 600 nm requires 𝑻𝑭𝑰𝑵 > 2 μm. From 𝑾𝑭𝑰𝑵 of 200 nm to 400 nm, DIBL (drain induced barrier lowering, i.e. Vₜₕ /Vds) increases by 300%, while from 400 to 600 nm, it rises by only 100%. -Qf increases breakdown voltage. Finally, β-Ga2O3 fin structures were fabricated to optimize etch profile.

6B.2 Final.2025

A novel long wavelength 1550 nm VCSEL structure is introduced utilizing an InP-based substrate and bottom DBR mirror, a dielectric silicon/silicon dioxide top DBR mirror, and a tunable phase-matching layer fabricated from a piezo-electric/electro-optic material. By applying a voltage bias across this phase-matching layer, the layer’s optical thickness can be altered, thereby shifting the overlap of the electric-field standing-wave pattern with
the gain region. When process variation/nonuniformity negatively impact the device performance, mainly threshold current and threshold modal gain, tuning of the
phase matching layer can optimize the standing wave overlap with the gain region, minimizing threshold current and modal gain. This work presents the novel
epitaxial structure designed and explores the viability of various materials for application as the phase-matching layer via simulation results utilizing the transfer-matrix method.

7A.5 Final.2025

Abstract
This study presents a model developed to analyze crack formation during the heteroepitaxial growth of ultrawide-bandgap (UWBG) III-N semiconductor films on Si substrates. It addresses the challenges of growing thick (~>1.5 μm) crack-free AlN films, which is crucial for integrating Si with UWBG semiconductors. Utilizing Griffith theory of brittle fracture and Mathews-Blakeslee theory of dislocations, the model predicts crack formation in 500-nm AlN films driven by in-plane tensile stress during the cool-down process after deposition. To prevent this, a ductile epitaxial interlayer is introduced to modify the tensile strain in the AlN film. This approach successfully demonstrates the epitaxial growth of 1.5-μm single-crystalline, crack-free AlN film on a Si substrate.

3B.5 Final.2025

ABSTRACT
Planar vertical gallium nitride devices are capable of utilizing the beneficial material properties inherent to bulk GaN without the interference of surface leakage pathways or passivation failures inherent to lateral devices, however, the stability and long-term viability of implanted termination necessitates study. Here we show  stressing of 3.3kV vertical GaN diodes with nitrogen implanted termination at over 80% of the breakdown voltage and at up to 200°C for over 400 hours. Some diodes exhibit a burn-in effect with small changes to the breakdown voltage and leakage at breakdown while others exhibit robust and nearly invariant behavior to the limits of testing. Additionally, thermal stressing of a cohort of devices without bias shows an increased degradation of breakdown voltage above 300°C and differentiation of devices within the cohort beyond 350°C enabling further study of the degradation mechanisms.

10B.3 Final.2025

Abstract
Silicon Carbide (SiC) power MOSFET performance depends on many key process and material properties. The drift layer active carrier concentration and thickness are important factors for defining device properties. Drift layer carrier concentration can be monitored easily by capacitance-voltage (CV) measurements. The leakage current (Ileak), breakdown voltage (VBD) and on-state resistivity (RON-sp) are all highly affected by control of the active carrier concentration profile and are monitorable by current-voltage (IV) measurements. Inadequate quality of the 4H-SiC epitaxial processes can degrade device performance and induce failure of the power MOSFET. In this paper, a high repeatability mercury probe is used to monitor these crucial electrical parameters and allows for a rapid response in improving and predicting final device behavior.

12.10 Final.2025

Abstract
At ATL, innovation drives the development of new technologies to meet customer needs, including in the semiconductor fabrication process. Shifts in processing can lead to issues like cross-contamination, impacting processes such as L-Band power transistor production. Residue left after photoresist strip processes caused concerns, affecting wafer quality and potentially leading to emitter-base shorts. Through a rigorous investigation and experimentation with different photoresist strip methods, a more effective approach using an alternate Asher tool was found. Implementing this new method significantly reduced residue, improving production yield and resolving process challenges in semiconductor manufacturing at ATL.

12.16 Final.2025

Abstract
Electron-beam (EB) evaporation systems are useful in forming thin metal films for the production of compound semiconductor devices. The formation of metal ballistic nodules during evaporation is a major concern because it degrades the production yield of wafers. These nodules are caused by high-melting-point materials and gaseous components in the evaporation source materials. In the production of Ag slugs for evaporation, these impurities are easily introduced during the casting of Ag ingots. To minimize the impurities, we propose implementing a new impurity removal process during casting and a new degassing process after cutting. The use of Ag slugs fabricated using these improved processes drastically reduces the number of particles on the wafer. Furthermore, by removing the impurities in the Ag slug, the amount of floating objects during evaporation, which inhibits evaporation, is reduced compared to using conventional Ag slugs. In addition, the use of low-contamination Ag slugs results in low EB emission during evaporation. These results indicate that low- impurity Ag slugs could be very effective not only for the deposition of uniform Ag thin films, but also for evaporation operations under more environmentally friendly conditions via EB evaporation in compound semiconductor devices and other applications.

11A.3 Final.2025

Abstract
Cost efficiency for data centers is providing an opportunity for quantum dot laser technology to move from a niche photonic process to a widely-adopted technology. This in turn drives the need for high-volume manufacturing methodologies in the production of QD epitaxial wafers. At the same time, integration of QDLs with Si photonics is an emerging focus. Epitaxy foundries such as IQE are drawing on their history of high-volume wafer manufacture to meet and manage the complexity associated with scaling QD epitaxy combined with end user device and integration needs. IQE is also able to leverage its capabilities to support next generation and emerging end user applications.

8A.1 Final.2025

Abstract
-Ga2O3 and its solid solutions -(AlxGa1-x)2O3 are considered as potential candidate materials for next generation power devices due to their ultra-wide bandgaps (4.85–5.6 eV) and large breakdown electric field ( 8 MVcm-1). Wafers prepared from bulk crystals constitute a foundation in a device fabrication chain. The present report briefly discusses challenges in growing bulk crystals by different methods, crystal structural quality, wafers, and electrical properties

3B.5 Final.2025

ABSTRACT
Planar vertical gallium nitride devices are capable of utilizing the beneficial material properties inherent to bulk GaN without the interference of surface leakage pathways or passivation failures inherent to lateral devices, however, the stability and long-term viability of implanted termination necessitates study. Here we show  stressing of 3.3kV vertical GaN diodes with nitrogen implanted termination at over 80% of the breakdown voltage and at up to 200°C for over 400 hours. Some diodes exhibit a burn-in effect with small changes to the breakdown voltage and leakage at breakdown while others exhibit robust and nearly invariant behavior to the limits of testing. Additionally, thermal stressing of a cohort of devices without bias shows an increased degradation of breakdown voltage above 300°C and differentiation of devices within the cohort beyond 350°C enabling further study of the degradation mechanisms.

10B.1 Final.2025

Abstract
Though wide bandgap semiconductors offer superior performance to its Si based counterpart, the current state of the art manufacturing technology produces several defects preventing devices from performing optimally. Particularly in SiC, the methods for detecting extended defects such as threading edge dislocations (TED), threading screw dislocations (TSD), basel plane dislocations (BPD), stacking faults, and polytype inclusions are well established; however, automated quantitative analysis is challenging due to the variable size, shape, and intensity of these numerous defects. This study focuses on developing machine learning models using multiple measurements with different techniques including x-ray topography (XRT) and ultraviolet photoluminescence (UVPL) to locate and quantify the microscopic defects on a macroscopic scale.

7A.5 Final.2025

Abstract
This study presents a model developed to analyze crack formation during the heteroepitaxial growth of ultrawide-bandgap (UWBG) III-N semiconductor films on Si substrates. It addresses the challenges of growing thick (~>1.5 μm) crack-free AlN films, which is crucial for integrating Si with UWBG semiconductors. Utilizing Griffith theory of brittle fracture and Mathews-Blakeslee theory of dislocations, the model predicts crack formation in 500-nm AlN films driven by in-plane tensile stress during the cool-down process after deposition. To prevent this, a ductile epitaxial interlayer is introduced to modify the tensile strain in the AlN film. This approach successfully demonstrates the epitaxial growth of 1.5-μm single-crystalline, crack-free AlN film on a Si substrate.

12.12 Final.2025

Abstract
Scaling interconnects to increase device density is a critical bottleneck for a range of applications in the 3D and advanced packaging fields. Currently, interconnect density is limited by, among other things, the ability to produce reliable, low resistivity Cu vias at high aspect ratios (AR). While some progress has been made, single side deposition, used in blind vias, is limited to 8:1 or 10:1. This limit is enforced by the adhesion and/or nucleation layer required for successful Cu electrochemical deposition (ECD). Current techniques provide high quality layers, but those layers are applied in a non-conformal fashion, leading to device failure at high AR or in reentrant features. Atomic layer deposition (ALD) is a vapor-phase deposition technique that can produce low resistivity metal films conformally over any feature accessible by process gas. In this work, we demonstrate successful Cu seed application by depositing a low-resistivity Ru metal film on Si trenches and through glass vias (TGV). Successful conformal ECD has been demonstrated with 10-20 nm of Ru in blind silicon vias with AR from 4:1 to 25:1 and in TGV with AR from 6:1 to 30:1. Further tests are ongoing to measure via resistivity after Cu ECD and to explore higher AR vias, such as 50:1.

7A.4 Final.2025

Abstract
The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Recently proton implantation has revealed its capability to block stacking fault expansion. We have evidenced through material characterization and electrical measurements of 1200 V PIN diodes that bipolar degradation can be mitigated above 1000 A/cm². A strong robustness has been evidenced through UV induced stacking faults. Electrical results are showing no visible bipolar degradation after a 600sec-2250 A/cm² stress test, while the reference material is showing a ~500mV drift at the device rated current of 10A.

7A.1 Final.2025

Abstract
In this work, we present the first demonstration of InP HBTs grown and fabricated on an engineered InPOSi substrate. Physical and electrical characterizations were performed to measure its crystal quality and device performance. We show that the performance of devices fabricated on an InPOSi substrate is close to devices fabricated on a native InP substrates making such a technology suitable for advanced RF applications. Fabricated devices show ft/fmax of ~140 GHz/70GHz with BVceo/BVcbo of 3.5 V/5.5 V at an ON current density of 8mA/μm2.

12.7 Final.2025

Abstract
We present and compare two methods for fabricating grating structures for photonic integrated circuits. The first method uses a two-step electron beam lithography (EBL) and dry etch process, while the second uses direct milling of the grating structures using focused ion beam (FIB) nanofabrication. In both cases 1st order periodic structures with a pitch of 238 nm were successfully positioned adjacent to the ridge waveguide. Using the EBL method, a final grating depth of 10 nm was observed with an estimated coupling coefficient of 40 cm-1. Direct milling using FIB provided grating features milled to a depth of up to 350 nm, achieving maximum coupling strengths of over 200 cm-1.

7A.4 Final.2025

Abstract
The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Recently proton implantation has revealed its capability to block stacking fault expansion. We have evidenced through material characterization and electrical measurements of 1200 V PIN diodes that bipolar degradation can be mitigated above 1000 A/cm². A strong robustness has been evidenced through UV induced stacking faults. Electrical results are showing no visible bipolar degradation after a 600sec-2250 A/cm² stress test, while the reference material is showing a ~500mV drift at the device rated current of 10A.

3A.4 Final.2025

Abstract
In this study we demonstrate that enhancement-mode behavior (Vₜₕ > 0) is achievable for β-Ga2O3 FinFET using a Fin width 𝑾𝑭𝑰𝑵≤0.5 μm and doping concentration 𝑵𝒅≤1×10¹⁶ cm⁻3. Breakdown voltage and output/transfer characteristics are calculated by using Drift-Diffusion methodology calibrated by experiments. We found that the metal work function (∅𝒎𝒔), dielectric constant (κ), and unintentional negative interface charge density (-Qf) at the β-Ga2O3/dielectric interface significantly impact Vₜₕ, with a high ∅𝒎𝒔 being necessary for enhancement mode operation. To achieve 5kV breakdown, a 𝑾𝑭𝑰𝑵 of 200 nm requires a fin thickness (𝑻𝑭𝑰𝑵) of 0.8 μm, a 𝑾𝑭𝑰𝑵 of 400 nm requires 𝑻𝑭𝑰𝑵> 1.2 μm, and a 𝑾𝑭𝑰𝑵 > 600 nm requires 𝑻𝑭𝑰𝑵 > 2 μm. From 𝑾𝑭𝑰𝑵 of 200 nm to 400 nm, DIBL (drain induced barrier lowering, i.e. Vₜₕ /Vds) increases by 300%, while from 400 to 600 nm, it rises by only 100%. -Qf increases breakdown voltage. Finally, β-Ga2O3 fin structures were fabricated to optimize etch profile.

4A.2 Final.2025

Abstract
We conducted DC and small-signal RF characterization on AlGaN/GaN high-electron-mobility transistors (HEMTs) over a range of temperatures to examine temperature-dependent variations in key device performance metrics including transconductance (gm), extrinsic cutoff frequency (fT), maximum gain frequency (fmax), unilateral power gain (UPG), and maximum stable gain (MSG). Our findings indicate that device parameters decline with increasing temperature at a distinct rate. Specifically, a 100°C rise results in fT and fmax dropping by about 8 GHz and 17 GHz, respectively, while MSG decreases by approximately 1 dB. These changes are inherent to the device physics and are not influenced by its geometry or operational mode.

3A.5 Final.2025

Abstract
Lateral p-GaN gate-based power HEMTs are fabricated using a 9 μm thick GaN buffer on 200 mm GaN-on-QST® engineered substrates with a poly-AlN core, targeting 1200 V applications. The fabricated devices on engineered p-GaN gate on 9 μm thick GaN buffer show good ON/OFF state electrical characteristics and breakdown ~ 1800 V. The reliability of the fabricated p-GaN HEMTs were evaluated by a 1000-hour high temperature reverse bias (HTRB) stress test at 1200 V. No impact of HTRB stress was observed on electrical parameters and the devices yield a high pass rate.

2A.3 Final.2025

Abstract
We present the performances of our GaN MISHEMTs, using a thin buffer grown on SiC substrate, to pave the way for lateral GaN devices to exploit power applications in the voltage range up to 1700 V. Uni- and bi-directional MISHEMTs based on gate and source-connected field plate, with LGD = 21 μm achieve a breakdown voltage over 1800 V at a drain-source and gate currents less than 50 nA/mm. The on-resistance of the 1 mm gate width uni- and bidirectional devices were 9.5 Ω∙mm and 13.5 Ω∙mm, respectively, with a specific on-resistance of 2.7 mΩ∙cm2 and 4.4 mΩ∙cm2, respectively. The 1mm single MISHEMT results in a high Baliga figure of merit (BFOM) of 1.2 GW/cm2. A 147 mm gate width MISHEMT delivered 20 A pulse IDS current, at VGS =0 V and VDS = 1.5 V. Moreover, the MISHEMTs feature encouraging and superior stand in the breakdown voltage vs. on-resistance benchmark to commercial devices. We addressed the potential of the GaN-HEMTs to cover

12.12 Final.2025

Abstract
Scaling interconnects to increase device density is a critical bottleneck for a range of applications in the 3D and advanced packaging fields. Currently, interconnect density is limited by, among other things, the ability to produce reliable, low resistivity Cu vias at high aspect ratios (AR). While some progress has been made, single side deposition, used in blind vias, is limited to 8:1 or 10:1. This limit is enforced by the adhesion and/or nucleation layer required for successful Cu electrochemical deposition (ECD). Current techniques provide high quality layers, but those layers are applied in a non-conformal fashion, leading to device failure at high AR or in reentrant features. Atomic layer deposition (ALD) is a vapor-phase deposition technique that can produce low resistivity metal films conformally over any feature accessible by process gas. In this work, we demonstrate successful Cu seed application by depositing a low-resistivity Ru metal film on Si trenches and through glass vias (TGV). Successful conformal ECD has been demonstrated with 10-20 nm of Ru in blind silicon vias with AR from 4:1 to 25:1 and in TGV with AR from 6:1 to 30:1. Further tests are ongoing to measure via resistivity after Cu ECD and to explore higher AR vias, such as 50:1.

7A.4 Final.2025

Abstract
The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Recently proton implantation has revealed its capability to block stacking fault expansion. We have evidenced through material characterization and electrical measurements of 1200 V PIN diodes that bipolar degradation can be mitigated above 1000 A/cm². A strong robustness has been evidenced through UV induced stacking faults. Electrical results are showing no visible bipolar degradation after a 600sec-2250 A/cm² stress test, while the reference material is showing a ~500mV drift at the device rated current of 10A.

10B.2 Final.2025

Abstract
This study presents a novel approach to device yield estimation based on the non-contact, corona-based QUAD(Quality, Uniformity, and Defects) technique for inline defect mapping in SiC epitaxial layers. The approach is applied to a merged PiN Schottky diode manufacturing process and is compared to final wafer level electrical data. A new analysis method for QUAD defect mapping is introduced, incorporating die yield bin maps based on indie depletion voltage values, allowing for a direct comparison with final electrical device performance. Micro-scale, QUAD and voltage data within each individual diode can gain further insight into the electrical nature of the defects causing the device failure. The results demonstrate a strong correlation between the inline QUAD bin map results and final device electrical properties, highlighting the potential of QUAD as a practical and powerful inline tool. This technique offers a complementary approach to UVPL defect imaging, identifying electrically active defects and enhancing estimations of the final production yield.

3B.5 Final.2025

ABSTRACT
Planar vertical gallium nitride devices are capable of utilizing the beneficial material properties inherent to bulk GaN without the interference of surface leakage pathways or passivation failures inherent to lateral devices, however, the stability and long-term viability of implanted termination necessitates study. Here we show  stressing of 3.3kV vertical GaN diodes with nitrogen implanted termination at over 80% of the breakdown voltage and at up to 200°C for over 400 hours. Some diodes exhibit a burn-in effect with small changes to the breakdown voltage and leakage at breakdown while others exhibit robust and nearly invariant behavior to the limits of testing. Additionally, thermal stressing of a cohort of devices without bias shows an increased degradation of breakdown voltage above 300°C and differentiation of devices within the cohort beyond 350°C enabling further study of the degradation mechanisms.

12.1 Final.2025

Abstract
ZnₓCd₁₋ₓTe (ZnCdTe) is a tunable II-VI semiconductor alloy with a direct bandgap energy ranging from 1.44 eV (CdTe) to 2.26 eV (ZnTe), making it a promising candidate for single-junction and tandem solar cells [1]. However, its performance is hindered by deep-level defects, such as cadmium vacancies and interstitials, which reduce carrier concentrations and lifetimes. While shallow-level doping is critical for optimizing conductivity, it remains underexplored in ZnCdTe[2]. This study investigates phosphorus (P) doping in ZnCdTe thin films grown on GaAs(100) substrates via molecular beam epitaxy (MBE), using Zn₃P₂ as the P source. By systematically varying the Zn₃P₂ flux, we examine the structural, optical, and electrical properties of P-doped ZnCdTe. The X-ray diffraction (XRD) reveals controlled Zn incorporation, while photoluminescence (PL) spectroscopy demonstrates bandgap tuning and defect mitigation.

3A.4 Final.2025

Abstract
In this study we demonstrate that enhancement-mode behavior (Vₜₕ > 0) is achievable for β-Ga2O3 FinFET using a Fin width 𝑾𝑭𝑰𝑵≤0.5 μm and doping concentration 𝑵𝒅≤1×10¹⁶ cm⁻3. Breakdown voltage and output/transfer characteristics are calculated by using Drift-Diffusion methodology calibrated by experiments. We found that the metal work function (∅𝒎𝒔), dielectric constant (κ), and unintentional negative interface charge density (-Qf) at the β-Ga2O3/dielectric interface significantly impact Vₜₕ, with a high ∅𝒎𝒔 being necessary for enhancement mode operation. To achieve 5kV breakdown, a 𝑾𝑭𝑰𝑵 of 200 nm requires a fin thickness (𝑻𝑭𝑰𝑵) of 0.8 μm, a 𝑾𝑭𝑰𝑵 of 400 nm requires 𝑻𝑭𝑰𝑵> 1.2 μm, and a 𝑾𝑭𝑰𝑵 > 600 nm requires 𝑻𝑭𝑰𝑵 > 2 μm. From 𝑾𝑭𝑰𝑵 of 200 nm to 400 nm, DIBL (drain induced barrier lowering, i.e. Vₜₕ /Vds) increases by 300%, while from 400 to 600 nm, it rises by only 100%. -Qf increases breakdown voltage. Finally, β-Ga2O3 fin structures were fabricated to optimize etch profile.

10A.3 Final.2025

Abstract
VCSEL layer structures are among the most complicated ones in compound semiconductor device production. Re-establishing growth conditions for a new epi campaign after chamber maintenance can be challenging and time consuming. This work is about how to tackle this challenge by applying in-situ optical metrology during growth and processing of GaAs-based VCSEL devices as well as post-growth ex-situ wafer mapping. We demonstrate how to efficiently combine in-situ and ex-situ white light reflectance (WLR) measurements and modelling in order to increase the target wavelength accuracy.
Fitting the in-situ reflectance transient or the ex-situ WLR is used to generate a target reflectance trace for the subsequent plasma etching of the VCSEL mesa enabling automated end pointing.

7A.2 Final.2025

Abstract
In this paper, we report 6-inch indium phosphide (InP) substrates with very low dislocation density produced using SEI’s Vertical Boat (VB) method. The growth conditions have been optimized to reduce crystal defects.

8A.3 Final.2025

Abstract
This study reports the melt growth of β-Ga2O3 single crystals using the Optical Floating Zone (OFZ) technique, and defect analysis in these wafers. X-ray diffraction (XRD) rocking curves show a full width at half maximum (FWHM) of 230 arcsec and the chemical mechanical polished surfaces exhibit a low surface roughness of 1.1 nm. Schottky barrier diodes (SBDs) were fabricated on these substrates and deep-level transient spectroscopy (DLTS) measurements were performed to investigate defects within the bandgap. DLTS analysis revealed a dominant single deep-level trap at 0.69 eV below the conduction band, attributed to Fe impurities from the source material used for melt-growth.

10B.3 Final.2025

Abstract
Silicon Carbide (SiC) power MOSFET performance depends on many key process and material properties. The drift layer active carrier concentration and thickness are important factors for defining device properties. Drift layer carrier concentration can be monitored easily by capacitance-voltage (CV) measurements. The leakage current (Ileak), breakdown voltage (VBD) and on-state resistivity (RON-sp) are all highly affected by control of the active carrier concentration profile and are monitorable by current-voltage (IV) measurements. Inadequate quality of the 4H-SiC epitaxial processes can degrade device performance and induce failure of the power MOSFET. In this paper, a high repeatability mercury probe is used to monitor these crucial electrical parameters and allows for a rapid response in improving and predicting final device behavior.

2A.4 Final.2025

Abstract

Vertical GaN MOSFETs are a promising technology for next generation efficient power systems. Here we investigate the effect of operating temperature on the on-state performance of quasi-vertical GaN MOSFETs, fabricated on SiC substrates. The threshold voltage, transconductance and on-resistance were extracted from measured characteristics across a range of temperatures. Shifts in both threshold voltage and transconductance are attributed to temperature dependent trapping-detrapping at the MOS interface. These are discussed in relation to series resistance contributions in the channel, drift layer and access resistances at the source and drain contacts.

12.10 Final.2025

Abstract
At ATL, innovation drives the development of new technologies to meet customer needs, including in the semiconductor fabrication process. Shifts in processing can lead to issues like cross-contamination, impacting processes such as L-Band power transistor production. Residue left after photoresist strip processes caused concerns, affecting wafer quality and potentially leading to emitter-base shorts. Through a rigorous investigation and experimentation with different photoresist strip methods, a more effective approach using an alternate Asher tool was found. Implementing this new method significantly reduced residue, improving production yield and resolving process challenges in semiconductor manufacturing at ATL.

12.12 Final.2025

Abstract
Scaling interconnects to increase device density is a critical bottleneck for a range of applications in the 3D and advanced packaging fields. Currently, interconnect density is limited by, among other things, the ability to produce reliable, low resistivity Cu vias at high aspect ratios (AR). While some progress has been made, single side deposition, used in blind vias, is limited to 8:1 or 10:1. This limit is enforced by the adhesion and/or nucleation layer required for successful Cu electrochemical deposition (ECD). Current techniques provide high quality layers, but those layers are applied in a non-conformal fashion, leading to device failure at high AR or in reentrant features. Atomic layer deposition (ALD) is a vapor-phase deposition technique that can produce low resistivity metal films conformally over any feature accessible by process gas. In this work, we demonstrate successful Cu seed application by depositing a low-resistivity Ru metal film on Si trenches and through glass vias (TGV). Successful conformal ECD has been demonstrated with 10-20 nm of Ru in blind silicon vias with AR from 4:1 to 25:1 and in TGV with AR from 6:1 to 30:1. Further tests are ongoing to measure via resistivity after Cu ECD and to explore higher AR vias, such as 50:1.

7A.2 Final.2025

Abstract
In this paper, we report 6-inch indium phosphide (InP) substrates with very low dislocation density produced using SEI’s Vertical Boat (VB) method. The growth conditions have been optimized to reduce crystal defects.

10B.4 Final.2025

As frequencies increase, the use of smaller value metal-insulator-metal (MIM) capacitors increases. For small capacitors, errors due to the bias of the top plate can cause significant errors. This bias is not correctly monitored with resistance based dW (RLWB) monitors. We present a simple capacitive based technique that uses only two test patterns to determine the value of the capacitive linewidth bias (CLWB) that is more appropriate for use electromagnetic (EM) simulation.

11B.2 Final.2025

Abstract
Design of experiments (DOE) were performed to optimize resistance uniformity for TaN thin film resistors (TFR) across the Ta target’s life cycle. Fine-tuned photo-lithography recipes with exposure dose compensation (DC) minimized resistance variation introduced during the resistor layer’s (RL) photolithography and deposition processes. Experimental studies revealed how critical dimensions (CD) are influenced by the photoresist’s chemical amplification, substrate’s thermal history during post-exposure bake (PEB), and the coupling time (CT) between process-sensitive steps. The implementation of additional process controls within the RL fabrication process enhanced process capability (Cpk), tightened statistical process control (SPC) of TaN-related electrical parameters, and improved probe yield.

11B.5 Final.2025

Abstract
In this work, the effects of emitter ledging on DC and RF performance in sub-micron InP DHBTs are investigated. We have demonstrated that incorporating a 160-nm emitter ledge leads to an over 100% increase in DC current gain (β), rising from 16 to 34. This gain increase is primarily due to the suppression of emitter peripheral surface recombination. However, increased emitter ledge also leads to a reduction in device high frequency fT and fMAX performance due to increase in device transit time and extrinsic resistance. Trade-off between enhanced beta gain and degraded RF bandwidth needs to be further studied on the emitter ledge length.

3B.3 Final.2025

Abstract
This paper presents a novel cavity coplanar waveguide (CCPW) structure based on GaN-on-SiC technology for high-power microwave applications. The CCPW structure was fabricated using an emerging monolithic microwave integrated circuit (MMIC)-compatible localised electrodeposition metal additive micro-manufacturing (μAM) process, achieving an air-bridge height of 50 μm. Electromagnetic (EM) simulations revealed that introducing a cavity above the CPW improves impedance matching at mm-wave frequencies while providing a robust ground-return path. S-parameter measurements show that the CCPW provides a 6.5 dB improvement in reflection coefficient at 110 GHz compared to a standard coplanar waveguide (CPW) structure. Furthermore, both simulations and measurements indicate a broadband reflection coefficient trough suggesting the potential for broadband impedance matching in MMIC applications. To further analyse RF parasitics, a high-frequency equivalent circuit model was developed, demonstrating significant performance improvements of the CCPW compared to a printed air-bridge.

10B.3 Final.2025

Abstract
Silicon Carbide (SiC) power MOSFET performance depends on many key process and material properties. The drift layer active carrier concentration and thickness are important factors for defining device properties. Drift layer carrier concentration can be monitored easily by capacitance-voltage (CV) measurements. The leakage current (Ileak), breakdown voltage (VBD) and on-state resistivity (RON-sp) are all highly affected by control of the active carrier concentration profile and are monitorable by current-voltage (IV) measurements. Inadequate quality of the 4H-SiC epitaxial processes can degrade device performance and induce failure of the power MOSFET. In this paper, a high repeatability mercury probe is used to monitor these crucial electrical parameters and allows for a rapid response in improving and predicting final device behavior.

2A.2 Final.2025

Abstract
In this study, vertical GaN trench MOSFETs were fabricated utilizing a novel gate dielectric composed of hafnium oxide (HfO₂) layered with aluminum oxide (Al₂O₃) to enhance device performance compared to those employing Al₂O₃ alone. The transistors incorporating the HfO₂ / Al₂O₃ layered gate dielectric exhibited up to three times increase in forward current, five times enhancement in gate breakdown voltage and significantly reduced threshold voltage shift induced by gate forward voltage stress, relative to devices with an Al₂O₃-only gate dielectric. Furthermore, the improved gate structure resulted in higher channel mobility (~11.1 cm²/Vs) and a reduced ON-state resistance (3.1 ± 0.6 mΩ·cm²).

3A.3 Final.2025

Abstract
In this study, we present vertical GaN based pn-diodes designed for high-voltage applications. These devices were initially grown and processed on 4-inch sapphire substrates and subsequently transferred to 4-inch tungsten substrates, enabling a fully vertical conduction path. Laser lift-off was employed to detach the GaN-membrane device structures from their original sapphire substrate. The diodes exhibit enhanced forward conduction following the transfer process, with the ON-state resistance decreasing from 1.52 ± 0.05 mΩcm2 to 1.15 ± 0.05 mΩcm2. During this time, the blocking strength remains largely unaffected, with its wafer level median value decreasing marginally from 1015 ± 47 V to 988 ± 57 V. The high device yields achieved through the membrane transfer procedure highlight the cost-competitiveness of this vertical GaN device technology for high-power applications, eliminating the need for expensive GaN substrates.

12.5 Final.2025

In this study, the reduction of contact resistance (Rc) in RF GaN HEMTs with an 8 nm Al₀.₃₆Ga₀.₆₄N barrier layer was investigated using two approaches: Si implantation and recess etching. Employing the Si implantation method with an optimized dopant activation procedure reduced Rc by 70% down to approximately 0.17 Ω·mm. In comparison, a reference alloyed Ti/Al/Ni/Au ohmic contact scheme without implantation achieved an Rc of ~0.60 Ω·mm. For the same epitaxial layer design, utilizing the recess etching technique reduced Rc by 50% down to 0.25 Ω·mm.

3B.5 Final.2025

ABSTRACT
Planar vertical gallium nitride devices are capable of utilizing the beneficial material properties inherent to bulk GaN without the interference of surface leakage pathways or passivation failures inherent to lateral devices, however, the stability and long-term viability of implanted termination necessitates study. Here we show  stressing of 3.3kV vertical GaN diodes with nitrogen implanted termination at over 80% of the breakdown voltage and at up to 200°C for over 400 hours. Some diodes exhibit a burn-in effect with small changes to the breakdown voltage and leakage at breakdown while others exhibit robust and nearly invariant behavior to the limits of testing. Additionally, thermal stressing of a cohort of devices without bias shows an increased degradation of breakdown voltage above 300°C and differentiation of devices within the cohort beyond 350°C enabling further study of the degradation mechanisms.

4B.4 Final.2025

Abstract
Herein, we demonstrate top, bottom, and double-side thermal management strategies for gallium nitride (GaN) high electron mobility transistors (HEMTs). The cooling technologies investigated include GaN/SiC (reference), GaN/diamond (bottom-side), diamond/GaN/SiC (top-side), and diamond/GaN/diamond (double-side). We review processing methods to realize these device structures as well as the intricacies of the fabrication process. From DC output characteristics, the diamond/GaN/diamond HEMTs demonstrate over 0.6 A/mm at VGS = 2 V. From a thermal perspective, the double-side diamond cooling approach enabled operation at DC power densities of ~30 W/mm with a peak temperature rise of ~50 K at the drain-side edge of the gate electrode. Finally, we demonstrate our initial efforts towards diamond encasement of AlGaN/GaN epilayers to further reduce device-level thermal resistance.

10B.1 Final.2025

Abstract
Though wide bandgap semiconductors offer superior performance to its Si based counterpart, the current state of the art manufacturing technology produces several defects preventing devices from performing optimally. Particularly in SiC, the methods for detecting extended defects such as threading edge dislocations (TED), threading screw dislocations (TSD), basel plane dislocations (BPD), stacking faults, and polytype inclusions are well established; however, automated quantitative analysis is challenging due to the variable size, shape, and intensity of these numerous defects. This study focuses on developing machine learning models using multiple measurements with different techniques including x-ray topography (XRT) and ultraviolet photoluminescence (UVPL) to locate and quantify the microscopic defects on a macroscopic scale.

5.1 Final.2025

DARPA’s Next-Generation Microelectronics Manufacturing program, known as NGMM, aims to unlock accessible prototyping for the microelectronics of tomorrow by establishing a national center for advancing U.S.-based 3D heterogeneous integration (3DHI). DARPA is working with The University of Texas at Austin, and its existing Texas Institute for Electronics (TIE) research center, to establish the TIE NGMM Center (TNC) to support 3DHI microelectronics research, development, and low-volume production. NGMM is leveraging partnerships spanning organizations across the defense industrial base, domestic foundries, vendors and startups, designers and manufacturers, members of academia, and other stakeholders to achieve a shared vision for national and economic security. By the program’s end, the center will be capable of producing high-performance 3DHI microsystems at reasonable cost, with cycle times supporting fast-paced innovative research.

10B.5 Final.2025

Abstract
Progress in Compound Semiconductors is hindered by the high level of defectivity of the initial material. Here we take Silicon Carbide manufacturing technology as an example and provide an overview of manufacturing analytics tools and methodologies used to drive yield ramp and capacity expansion. We focus on 2 examples of siteto- site handoff: substrates handoff to IC front-end fab or foundry and wafer hand-off to the assembly and test site. Holistic end-to-end yield management is enabled by deploying Big Data platform at the enterprise level. This framework applies to both fabless companies and IDM’s. It also extends to a fully outsourced, fully vertically integrated IDM and anything in between.

6B.3 Final.2025

Abstract
Polar Light Technologies has developed an innovative microLED solution that generates RGB emission within a single material system, achieving a significant leap in microLED technology, especially for micro-projector and display applications. By employing a unique bottom-up approach based on hexagonal GaN pyramids with InGaN quantum wells (QW), microLEDs with dominant emission at 470 nm, 520 nm and 625 nm were demonstrated without the need for separate phosphor or quantum dot color conversion. This integration will not only simplify the future manufacturing process but also enhances the color uniformity and stability throughout a device.

10B.3 Final.2025

Abstract
Silicon Carbide (SiC) power MOSFET performance depends on many key process and material properties. The drift layer active carrier concentration and thickness are important factors for defining device properties. Drift layer carrier concentration can be monitored easily by capacitance-voltage (CV) measurements. The leakage current (Ileak), breakdown voltage (VBD) and on-state resistivity (RON-sp) are all highly affected by control of the active carrier concentration profile and are monitorable by current-voltage (IV) measurements. Inadequate quality of the 4H-SiC epitaxial processes can degrade device performance and induce failure of the power MOSFET. In this paper, a high repeatability mercury probe is used to monitor these crucial electrical parameters and allows for a rapid response in improving and predicting final device behavior.

12.14 Final.2025

Abstract
Defects known as “craters” because of their resemblance to actual craters (Fig. 1) can cause scrap events, lower die yields, and increased cycle time due to the necessary process reworks to remove the defect source. Affected wafers exhibit a delaminated metal seed layer along the defect site, resulting in inconsistent gold plating atop the seed layer (Fig. 2). Without a uniform plated-gold layer, wafers must either be scrapped or reworked due to increased risk of copper migration through the collector layer [1].
Crater defect formation has been revealed with the help of cross-sectional SEM (Scanning Electron Microscope) using FIB (Focused Ion Beam). A pinhole is created through the seed layer being deposited atop a particle. The pinhole enables NH4OH to galvanically corrode the underlying metal within the multi-metallic seed layer during the pre-plating clean. This galvanic corrosion of the seed layer then causes nonuniform gold plating. Leveraging this finding, it is explored how modifying this pre-clean step can significantly reduce crater defect prevalence, as with the seed layer more intact, gold plating remains uniform.
Through this multi-faceted approach, both the prevalence and impact of crater defects is reduced through halting the frequency of initial pinhole formation and mitigating the impact of the subsequent galvanic corrosion.

12.18 Final.2025

Abstract
This material presents the technology development on 0.25um GaN High Electron Mobility Transistor (HEMT) on Silicon in WAVETEK Microelectronics. Epitaxy, process, BVD and RF characteristics are included in this material. The first process flow is designed for averaged power ≤ 20W and operation voltage@28V diverse power amplifier (PA) applications, e.g. massive MIMO basestation PA or phase array radar. DC performance of 4x100um device showed breakdown voltage > 200V. And RF results show fT, fmax (Vd=28V) = 28, 95 GHz, respectively. MSG/MAG= 23 dB @Vd= 28V and frequency= 3.5GHz. With optimized epitaxy structure and process, current collapse has been improved to 11.3%. Based on continuous wave (CW) load-pull measurement with harmonic tuning, (Vd=28V, Jc=20mA/mm, @3.5GHz), PAE@P3dB can achieve 70%, Gain= 19dB and Pout@P3dB can reach 32 dBm. For the other application of Vd=10V, e.g. WiFi Router PA and direct to cell PA, the 0.4mm HEMT device can achieve 2.1W. Adjacent Channel Leakage Ratio (ACLR) has been measured. The 4x100um HEMT results of raw ACPR (without DPD) are -39.3dBc/-38.6dBc. The overall performance is promising for 0.25um GaN on Silicon technology. The overall performance is promising for 0.25um GaN on Silicon technology.

6B.3 Final.2025

Abstract
Polar Light Technologies has developed an innovative microLED solution that generates RGB emission within a single material system, achieving a significant leap in microLED technology, especially for micro-projector and display applications. By employing a unique bottom-up approach based on hexagonal GaN pyramids with InGaN quantum wells (QW), microLEDs with dominant emission at 470 nm, 520 nm and 625 nm were demonstrated without the need for separate phosphor or quantum dot color conversion. This integration will not only simplify the future manufacturing process but also enhances the color uniformity and stability throughout a device.

8A.2 Final.2025

Abstract
This work presents β-Ga2O3 trench Schottky barrier diodes (TSBDs) with double drift layer structures, achieving a 34% lower on-resistance compared to conventional single drift layer structures, without compromising the off-state performance. The TSBDs exhibit a breakdown voltage of ~2.4 kV, after which the devices were observed to crack along the [010] crystallographic direction in β-Ga2O3. The mechanisms behind breakdown-induced cracking were investigated including using nanoindentation, which revealed that the cracking is due to relatively weak chemical bonding along the [010] direction.

2B.3 Final.2025

Abstract
This report investigates 940 nm vertical-cavity surface-emitting lasers (VCSELs) with three junctions (3J). The study focuses on the impact of oxide layers on the electrical and optical performance of these devices under various pulse conditions. Heat accumulation is a significant challenge in VCSELs, and shorter pulse durations reduce heat generation, improving thermal performance and minimizing lateral carrier diffusion in multi-junction structures. The results indicate that incorporating multiple oxide layers enhances carrier confinement, enabling output power exceeding 120 watts with 1.6-nanosecond pulses. However, using a single oxide layer decreases resistance and improves thermal dissipation, while maintaining output power above 100 watts. Spectral measurements revealed a red shift of less than 0.8 nm, corresponding to temperature variations of less than 12°C at 40A current injection. These findings provide valuable insights into the benefits and limitations of multi-junction VCSELs for next-generation sensing applications.

2B.3 Final.2025

Abstract
This report investigates 940 nm vertical-cavity surface-emitting lasers (VCSELs) with three junctions (3J). The study focuses on the impact of oxide layers on the electrical and optical performance of these devices under various pulse conditions. Heat accumulation is a significant challenge in VCSELs, and shorter pulse durations reduce heat generation, improving thermal performance and minimizing lateral carrier diffusion in multi-junction structures. The results indicate that incorporating multiple oxide layers enhances carrier confinement, enabling output power exceeding 120 watts with 1.6-nanosecond pulses. However, using a single oxide layer decreases resistance and improves thermal dissipation, while maintaining output power above 100 watts. Spectral measurements revealed a red shift of less than 0.8 nm, corresponding to temperature variations of less than 12°C at 40A current injection. These findings provide valuable insights into the benefits and limitations of multi-junction VCSELs for next-generation sensing applications.

4A.2 Final.2025

Abstract
We conducted DC and small-signal RF characterization on AlGaN/GaN high-electron-mobility transistors (HEMTs) over a range of temperatures to examine temperature-dependent variations in key device performance metrics including transconductance (gm), extrinsic cutoff frequency (fT), maximum gain frequency (fmax), unilateral power gain (UPG), and maximum stable gain (MSG). Our findings indicate that device parameters decline with increasing temperature at a distinct rate. Specifically, a 100°C rise results in fT and fmax dropping by about 8 GHz and 17 GHz, respectively, while MSG decreases by approximately 1 dB. These changes are inherent to the device physics and are not influenced by its geometry or operational mode.

3A.4 Final.2025

Abstract
In this study we demonstrate that enhancement-mode behavior (Vₜₕ > 0) is achievable for β-Ga2O3 FinFET using a Fin width 𝑾𝑭𝑰𝑵≤0.5 μm and doping concentration 𝑵𝒅≤1×10¹⁶ cm⁻3. Breakdown voltage and output/transfer characteristics are calculated by using Drift-Diffusion methodology calibrated by experiments. We found that the metal work function (∅𝒎𝒔), dielectric constant (κ), and unintentional negative interface charge density (-Qf) at the β-Ga2O3/dielectric interface significantly impact Vₜₕ, with a high ∅𝒎𝒔 being necessary for enhancement mode operation. To achieve 5kV breakdown, a 𝑾𝑭𝑰𝑵 of 200 nm requires a fin thickness (𝑻𝑭𝑰𝑵) of 0.8 μm, a 𝑾𝑭𝑰𝑵 of 400 nm requires 𝑻𝑭𝑰𝑵> 1.2 μm, and a 𝑾𝑭𝑰𝑵 > 600 nm requires 𝑻𝑭𝑰𝑵 > 2 μm. From 𝑾𝑭𝑰𝑵 of 200 nm to 400 nm, DIBL (drain induced barrier lowering, i.e. Vₜₕ /Vds) increases by 300%, while from 400 to 600 nm, it rises by only 100%. -Qf increases breakdown voltage. Finally, β-Ga2O3 fin structures were fabricated to optimize etch profile.

10B.5 Final.2025

Abstract
Progress in Compound Semiconductors is hindered by the high level of defectivity of the initial material. Here we take Silicon Carbide manufacturing technology as an example and provide an overview of manufacturing analytics tools and methodologies used to drive yield ramp and capacity expansion. We focus on 2 examples of siteto- site handoff: substrates handoff to IC front-end fab or foundry and wafer hand-off to the assembly and test site. Holistic end-to-end yield management is enabled by deploying Big Data platform at the enterprise level. This framework applies to both fabless companies and IDM’s. It also extends to a fully outsourced, fully vertically integrated IDM and anything in between.

4A.2 Final.2025

Abstract
We conducted DC and small-signal RF characterization on AlGaN/GaN high-electron-mobility transistors (HEMTs) over a range of temperatures to examine temperature-dependent variations in key device performance metrics including transconductance (gm), extrinsic cutoff frequency (fT), maximum gain frequency (fmax), unilateral power gain (UPG), and maximum stable gain (MSG). Our findings indicate that device parameters decline with increasing temperature at a distinct rate. Specifically, a 100°C rise results in fT and fmax dropping by about 8 GHz and 17 GHz, respectively, while MSG decreases by approximately 1 dB. These changes are inherent to the device physics and are not influenced by its geometry or operational mode.

4B.4 Final.2025

Abstract
Herein, we demonstrate top, bottom, and double-side thermal management strategies for gallium nitride (GaN) high electron mobility transistors (HEMTs). The cooling technologies investigated include GaN/SiC (reference), GaN/diamond (bottom-side), diamond/GaN/SiC (top-side), and diamond/GaN/diamond (double-side). We review processing methods to realize these device structures as well as the intricacies of the fabrication process. From DC output characteristics, the diamond/GaN/diamond HEMTs demonstrate over 0.6 A/mm at VGS = 2 V. From a thermal perspective, the double-side diamond cooling approach enabled operation at DC power densities of ~30 W/mm with a peak temperature rise of ~50 K at the drain-side edge of the gate electrode. Finally, we demonstrate our initial efforts towards diamond encasement of AlGaN/GaN epilayers to further reduce device-level thermal resistance.

10B.3 Final.2025

Abstract
Silicon Carbide (SiC) power MOSFET performance depends on many key process and material properties. The drift layer active carrier concentration and thickness are important factors for defining device properties. Drift layer carrier concentration can be monitored easily by capacitance-voltage (CV) measurements. The leakage current (Ileak), breakdown voltage (VBD) and on-state resistivity (RON-sp) are all highly affected by control of the active carrier concentration profile and are monitorable by current-voltage (IV) measurements. Inadequate quality of the 4H-SiC epitaxial processes can degrade device performance and induce failure of the power MOSFET. In this paper, a high repeatability mercury probe is used to monitor these crucial electrical parameters and allows for a rapid response in improving and predicting final device behavior.

2A.4 Final.2025

Abstract

Vertical GaN MOSFETs are a promising technology for next generation efficient power systems. Here we investigate the effect of operating temperature on the on-state performance of quasi-vertical GaN MOSFETs, fabricated on SiC substrates. The threshold voltage, transconductance and on-resistance were extracted from measured characteristics across a range of temperatures. Shifts in both threshold voltage and transconductance are attributed to temperature dependent trapping-detrapping at the MOS interface. These are discussed in relation to series resistance contributions in the channel, drift layer and access resistances at the source and drain contacts.

3A.4 Final.2025

Abstract
In this study we demonstrate that enhancement-mode behavior (Vₜₕ > 0) is achievable for β-Ga2O3 FinFET using a Fin width 𝑾𝑭𝑰𝑵≤0.5 μm and doping concentration 𝑵𝒅≤1×10¹⁶ cm⁻3. Breakdown voltage and output/transfer characteristics are calculated by using Drift-Diffusion methodology calibrated by experiments. We found that the metal work function (∅𝒎𝒔), dielectric constant (κ), and unintentional negative interface charge density (-Qf) at the β-Ga2O3/dielectric interface significantly impact Vₜₕ, with a high ∅𝒎𝒔 being necessary for enhancement mode operation. To achieve 5kV breakdown, a 𝑾𝑭𝑰𝑵 of 200 nm requires a fin thickness (𝑻𝑭𝑰𝑵) of 0.8 μm, a 𝑾𝑭𝑰𝑵 of 400 nm requires 𝑻𝑭𝑰𝑵> 1.2 μm, and a 𝑾𝑭𝑰𝑵 > 600 nm requires 𝑻𝑭𝑰𝑵 > 2 μm. From 𝑾𝑭𝑰𝑵 of 200 nm to 400 nm, DIBL (drain induced barrier lowering, i.e. Vₜₕ /Vds) increases by 300%, while from 400 to 600 nm, it rises by only 100%. -Qf increases breakdown voltage. Finally, β-Ga2O3 fin structures were fabricated to optimize etch profile.

7A.5 Final.2025

Abstract
This study presents a model developed to analyze crack formation during the heteroepitaxial growth of ultrawide-bandgap (UWBG) III-N semiconductor films on Si substrates. It addresses the challenges of growing thick (~>1.5 μm) crack-free AlN films, which is crucial for integrating Si with UWBG semiconductors. Utilizing Griffith theory of brittle fracture and Mathews-Blakeslee theory of dislocations, the model predicts crack formation in 500-nm AlN films driven by in-plane tensile stress during the cool-down process after deposition. To prevent this, a ductile epitaxial interlayer is introduced to modify the tensile strain in the AlN film. This approach successfully demonstrates the epitaxial growth of 1.5-μm single-crystalline, crack-free AlN film on a Si substrate.

12.7 Final.2025

Abstract
We present and compare two methods for fabricating grating structures for photonic integrated circuits. The first method uses a two-step electron beam lithography (EBL) and dry etch process, while the second uses direct milling of the grating structures using focused ion beam (FIB) nanofabrication. In both cases 1st order periodic structures with a pitch of 238 nm were successfully positioned adjacent to the ridge waveguide. Using the EBL method, a final grating depth of 10 nm was observed with an estimated coupling coefficient of 40 cm-1. Direct milling using FIB provided grating features milled to a depth of up to 350 nm, achieving maximum coupling strengths of over 200 cm-1.

11A.1 Final.2025

Abstract – The utilization of electron beam lithography (EBL) as a wafer scale technique for the fabrication of compound semiconductor devices provides unique challenges in terms of both application and throughput. We report on wafer scale EBL in the context of fabricating edge emitting lasers on 150mm indium phosphide (InP) substrates. A hybrid electro-optical lithography process is used to pattern typical ridge waveguide (RWG) laser structures, while overcoming some of the practical challenges associated with fabricating these devices on large wafer platforms.

10B.2 Final.2025

Abstract
This study presents a novel approach to device yield estimation based on the non-contact, corona-based QUAD(Quality, Uniformity, and Defects) technique for inline defect mapping in SiC epitaxial layers. The approach is applied to a merged PiN Schottky diode manufacturing process and is compared to final wafer level electrical data. A new analysis method for QUAD defect mapping is introduced, incorporating die yield bin maps based on indie depletion voltage values, allowing for a direct comparison with final electrical device performance. Micro-scale, QUAD and voltage data within each individual diode can gain further insight into the electrical nature of the defects causing the device failure. The results demonstrate a strong correlation between the inline QUAD bin map results and final device electrical properties, highlighting the potential of QUAD as a practical and powerful inline tool. This technique offers a complementary approach to UVPL defect imaging, identifying electrically active defects and enhancing estimations of the final production yield.

4A.1 Final.2025

Abstract
We developed high-power and high-reliability quaternary InAlGaN/GaN HEMTs via TCVD SiNx passivation. This passivation technique achieves lower sheet resistance and higher-voltage operation for an InAlGaN/GaN HEMT compared with PECVD SiNx passivation. Moreover, it yields a record-high output power density of 31.0 W/mm in the X-band. Furthermore, we demonstrated that the InAlGaN/GaN HEMT with TCVD SiNx passivation is highly reliable.

4A.4 Final.2025

Abstract
E-mode p-GaN -gate RF HEMT with engineered Mg doping profile was developed and demonstrated for high power amplifier application. Through the design of a low-temperature MOCVD Mg doping profile and a reduction in Mg doping concentration, the diffusion of Mg into AlGaN is minimized compared to traditionally high Mg-doping grown p-GaN. This design enhances the gate modulation capability of p-GaN for RF applications, resulting in a higher gm peak. In addition, the Poole–Frenkel (PF) tunneling induced flicker noise was also suppressed at high input power swing due to low inactivated Mg induced traps. With the engineered Mg-doping profile design, a 61.4 % PAE was achieved together with an output power density close to 1 W/mm at VDS of 10 V which exhibit a highly potential for satellite direct-to-cell and FR3 mobile phone single voltage supply PA applications.

3B.5 Final.2025

ABSTRACT
Planar vertical gallium nitride devices are capable of utilizing the beneficial material properties inherent to bulk GaN without the interference of surface leakage pathways or passivation failures inherent to lateral devices, however, the stability and long-term viability of implanted termination necessitates study. Here we show  stressing of 3.3kV vertical GaN diodes with nitrogen implanted termination at over 80% of the breakdown voltage and at up to 200°C for over 400 hours. Some diodes exhibit a burn-in effect with small changes to the breakdown voltage and leakage at breakdown while others exhibit robust and nearly invariant behavior to the limits of testing. Additionally, thermal stressing of a cohort of devices without bias shows an increased degradation of breakdown voltage above 300°C and differentiation of devices within the cohort beyond 350°C enabling further study of the degradation mechanisms.

10B.2 Final.2025

Abstract
This study presents a novel approach to device yield estimation based on the non-contact, corona-based QUAD(Quality, Uniformity, and Defects) technique for inline defect mapping in SiC epitaxial layers. The approach is applied to a merged PiN Schottky diode manufacturing process and is compared to final wafer level electrical data. A new analysis method for QUAD defect mapping is introduced, incorporating die yield bin maps based on indie depletion voltage values, allowing for a direct comparison with final electrical device performance. Micro-scale, QUAD and voltage data within each individual diode can gain further insight into the electrical nature of the defects causing the device failure. The results demonstrate a strong correlation between the inline QUAD bin map results and final device electrical properties, highlighting the potential of QUAD as a practical and powerful inline tool. This technique offers a complementary approach to UVPL defect imaging, identifying electrically active defects and enhancing estimations of the final production yield.

12.2 Final.2025

Abstract
RF-plasma assisted nitridation was used to transform (100) -Ga2O3 to (0001) wurtzite GaN and subsequently grow a 520 nm p-GaN cap layer over 5 intervals. The final step involved a 11.5 hour anneal at the growth temperature of 680 C to allow for equilibration inside the crystal body. The nitridated film was characterized via X-ray diffraction (XRD), which revealed peaks distinct from the (0001) family. Analysis of these distinct peaks revealed varying (𝒉𝟎𝒍) orientations. We theorize that the alternate orientations are forming to accommodate the growing GaN film, gradually shifting towards the ideal heteroepitaxy plane of (𝟐̅𝟎𝟏). XRD rocking curves of the (0002) GaN were used to analyze crystallinity as a function of thickness. Results showed a transformation at the 120 nm interval, from a single Gaussian-like peak to a broad-narrow dual peak configuration. The FWHM’s were extracted and plotted against a previous study, indicating narrower, improved peak of 20%.

12.3 Final.2025

Abstract
Silicon nitride shadowed selective area growth (SNS-SAG) for homoepitaxy of GaN via RF plasma-assisted molecular beam epitaxy (PAMBE) has been shown to avoid the defects that arise from conventional selective area processing methods such as inductively coupled plasma reactive ion etching (ICP-RIE) and ion implantation. This work investigates the extension of this method to improve the heteroepitaxy of GaN on β-Ga2O3 by modifying the makeup of the SNS-SAG mask. Gallium rich and nitrogen rich GaN films are grown with SNS-SAG masks on β-Ga2O3 substrates. While current device performance has yet to be optimized, the adapted SNS-SAG mask retains both function and structural integrity as shown by scanning electron microscopy (SEM).

10B.3 Final.2025

Abstract
Silicon Carbide (SiC) power MOSFET performance depends on many key process and material properties. The drift layer active carrier concentration and thickness are important factors for defining device properties. Drift layer carrier concentration can be monitored easily by capacitance-voltage (CV) measurements. The leakage current (Ileak), breakdown voltage (VBD) and on-state resistivity (RON-sp) are all highly affected by control of the active carrier concentration profile and are monitorable by current-voltage (IV) measurements. Inadequate quality of the 4H-SiC epitaxial processes can degrade device performance and induce failure of the power MOSFET. In this paper, a high repeatability mercury probe is used to monitor these crucial electrical parameters and allows for a rapid response in improving and predicting final device behavior.

12.2 Final.2025

Abstract
RF-plasma assisted nitridation was used to transform (100) -Ga2O3 to (0001) wurtzite GaN and subsequently grow a 520 nm p-GaN cap layer over 5 intervals. The final step involved a 11.5 hour anneal at the growth temperature of 680 C to allow for equilibration inside the crystal body. The nitridated film was characterized via X-ray diffraction (XRD), which revealed peaks distinct from the (0001) family. Analysis of these distinct peaks revealed varying (𝒉𝟎𝒍) orientations. We theorize that the alternate orientations are forming to accommodate the growing GaN film, gradually shifting towards the ideal heteroepitaxy plane of (𝟐̅𝟎𝟏). XRD rocking curves of the (0002) GaN were used to analyze crystallinity as a function of thickness. Results showed a transformation at the 120 nm interval, from a single Gaussian-like peak to a broad-narrow dual peak configuration. The FWHM’s were extracted and plotted against a previous study, indicating narrower, improved peak of 20%.

12.3 Final.2025

Abstract
Silicon nitride shadowed selective area growth (SNS-SAG) for homoepitaxy of GaN via RF plasma-assisted molecular beam epitaxy (PAMBE) has been shown to avoid the defects that arise from conventional selective area processing methods such as inductively coupled plasma reactive ion etching (ICP-RIE) and ion implantation. This work investigates the extension of this method to improve the heteroepitaxy of GaN on β-Ga2O3 by modifying the makeup of the SNS-SAG mask. Gallium rich and nitrogen rich GaN films are grown with SNS-SAG masks on β-Ga2O3 substrates. While current device performance has yet to be optimized, the adapted SNS-SAG mask retains both function and structural integrity as shown by scanning electron microscopy (SEM).

7A.5 Final.2025

Abstract
This study presents a model developed to analyze crack formation during the heteroepitaxial growth of ultrawide-bandgap (UWBG) III-N semiconductor films on Si substrates. It addresses the challenges of growing thick (~>1.5 μm) crack-free AlN films, which is crucial for integrating Si with UWBG semiconductors. Utilizing Griffith theory of brittle fracture and Mathews-Blakeslee theory of dislocations, the model predicts crack formation in 500-nm AlN films driven by in-plane tensile stress during the cool-down process after deposition. To prevent this, a ductile epitaxial interlayer is introduced to modify the tensile strain in the AlN film. This approach successfully demonstrates the epitaxial growth of 1.5-μm single-crystalline, crack-free AlN film on a Si substrate.

4B.2 Final.2025

Abstract
This paper discusses Qorvo’s recent release of Cu Pillar (CuP) interconnect technology with Ni barrier on high frequency Gallium Nitride (GaN) HEMTs fabricated on Silicon Carbide (SiC) 150 mm substrates. Ongoing multi-temperature High Temperature Storage (HTS) tests indicate > 2×106 h median lifetime for CuP joints at 85ºC. Different types of CuP Ni plating are being studied which display a difference in lifetimes. Results demonstrate the use of ENEPIG finish on the laminate substrates could further increase CuP solder-joint reliability, allowing their use at temperatures up to 125ºC.

2A.3 Final.2025

Abstract
We present the performances of our GaN MISHEMTs, using a thin buffer grown on SiC substrate, to pave the way for lateral GaN devices to exploit power applications in the voltage range up to 1700 V. Uni- and bi-directional MISHEMTs based on gate and source-connected field plate, with LGD = 21 μm achieve a breakdown voltage over 1800 V at a drain-source and gate currents less than 50 nA/mm. The on-resistance of the 1 mm gate width uni- and bidirectional devices were 9.5 Ω∙mm and 13.5 Ω∙mm, respectively, with a specific on-resistance of 2.7 mΩ∙cm2 and 4.4 mΩ∙cm2, respectively. The 1mm single MISHEMT results in a high Baliga figure of merit (BFOM) of 1.2 GW/cm2. A 147 mm gate width MISHEMT delivered 20 A pulse IDS current, at VGS =0 V and VDS = 1.5 V. Moreover, the MISHEMTs feature encouraging and superior stand in the breakdown voltage vs. on-resistance benchmark to commercial devices. We addressed the potential of the GaN-HEMTs to cover

11A.4 Final.2025

Abstract
In this work, the development of solar-blind ultraviolet detectors based on the AlGaN materials system is discussed. This development includes design, growth, characterization, fabrication, and packaging of devices in a vertically integrated environment. The advantage of keeping all major steps needed to realize the devices in-house is discussed with focus on process control and holistic device manufacturing. Finally, device properties including sensitivity and efficiency are presented and an outlook on future developments is given.

6A.2 Final.2025

Abstract
We demonstrate the heterogeneous integration of SWIR large-area InGaAs photodetectors and pixelated photodetector arrays on 300 mm CMOS-compatible Si (100) substrates through direct heteroepitaxy. The devices exhibit low dark current, high responsivity, low capacitance, and high quantum efficiency at shortwave infrared wavelengths.

3B.5 Final.2025

ABSTRACT
Planar vertical gallium nitride devices are capable of utilizing the beneficial material properties inherent to bulk GaN without the interference of surface leakage pathways or passivation failures inherent to lateral devices, however, the stability and long-term viability of implanted termination necessitates study. Here we show  stressing of 3.3kV vertical GaN diodes with nitrogen implanted termination at over 80% of the breakdown voltage and at up to 200°C for over 400 hours. Some diodes exhibit a burn-in effect with small changes to the breakdown voltage and leakage at breakdown while others exhibit robust and nearly invariant behavior to the limits of testing. Additionally, thermal stressing of a cohort of devices without bias shows an increased degradation of breakdown voltage above 300°C and differentiation of devices within the cohort beyond 350°C enabling further study of the degradation mechanisms.

4B.4 Final.2025

Abstract
Herein, we demonstrate top, bottom, and double-side thermal management strategies for gallium nitride (GaN) high electron mobility transistors (HEMTs). The cooling technologies investigated include GaN/SiC (reference), GaN/diamond (bottom-side), diamond/GaN/SiC (top-side), and diamond/GaN/diamond (double-side). We review processing methods to realize these device structures as well as the intricacies of the fabrication process. From DC output characteristics, the diamond/GaN/diamond HEMTs demonstrate over 0.6 A/mm at VGS = 2 V. From a thermal perspective, the double-side diamond cooling approach enabled operation at DC power densities of ~30 W/mm with a peak temperature rise of ~50 K at the drain-side edge of the gate electrode. Finally, we demonstrate our initial efforts towards diamond encasement of AlGaN/GaN epilayers to further reduce device-level thermal resistance.

6A.3 Final.2025

Abstract
This paper presents Circuits Integrated Hellas’s (CIH) innovative use of III-V compound semiconductors with advanced 3D packaging. CIH introduces disruptive, high-performance solutions for satellite communication (SatCom) applications, leveraging System-in-Package (SiP) and Antenna-in-Package (AiP) methodologies. These approaches minimize the weight, volume, and cost of flat-panel phased array antennas, addressing a critical need in modern space communications

12.16 Final.2025

Abstract
Electron-beam (EB) evaporation systems are useful in forming thin metal films for the production of compound semiconductor devices. The formation of metal ballistic nodules during evaporation is a major concern because it degrades the production yield of wafers. These nodules are caused by high-melting-point materials and gaseous components in the evaporation source materials. In the production of Ag slugs for evaporation, these impurities are easily introduced during the casting of Ag ingots. To minimize the impurities, we propose implementing a new impurity removal process during casting and a new degassing process after cutting. The use of Ag slugs fabricated using these improved processes drastically reduces the number of particles on the wafer. Furthermore, by removing the impurities in the Ag slug, the amount of floating objects during evaporation, which inhibits evaporation, is reduced compared to using conventional Ag slugs. In addition, the use of low-contamination Ag slugs results in low EB emission during evaporation. These results indicate that low- impurity Ag slugs could be very effective not only for the deposition of uniform Ag thin films, but also for evaporation operations under more environmentally friendly conditions via EB evaporation in compound semiconductor devices and other applications.

12.17 Final.2025

Abstract
For high-performance GaN-based transistors, minimizing contact resistance is essential to reduce power losses and enhance switching efficiency. Achieving highly- doped contact areas in GaN is challenging due to its high binding energy and self-compensation effects. This study investigates the electrical activation of silicon-implanted GaN-on-sapphire structures using rapid thermal annealing (RTA) and optimized cap layers. Various cap materials, including sputtered and PECVD SiNx, Al2O3, and bilayer approaches, were evaluated for their ability to prevent GaN decomposition during high-temperature annealing. The best-performing cap consisted of a 10 nm thick CVD SiNx layer followed by 10 nm ALD Al2O3 layer, providing effective surface protection up to 1300 °C. Sheet resistance measurements indicate that higher annealing temperatures and optimized spike annealing conditions improve dopant activation, with the lowest sheet resistance of 188 Ω/□ achieved at 1400 °C using a two-spike process. These findings provide insights into optimizing thermal processes for high-performance GaN device fabrication.

10A.4 Final.2025

2D-VCSEL arrays utilizing elliptical disorder-defined apertures for simultaneous single-mode, singlepolarization operation are demonstrated. Optical losses induced by the disordered region in the periphery of the VCSEL suppress the capability of higher-order modes from lasing, achieving single-fundamental mode
operation. Furthermore, introducing eccentricity to the aperture creates an asymmetric threshold gain, or dichroism, that selectively suppresses one of the two polarization states inherent to VCSELs, resulting in single-polarization operation. The work presented here discusses the design, fabrication, and characterization results of the 2D-VCSEL arrays. The arrays are characterized for optical output power, single-mode performance via optical spectra measurements, and single-polarization performance via polarization-resolved light-current-voltage (PR-LIV) curves.

6A.4 Final.2025

Abstract
This paper presents the thermal benefits of a heterogeneous integration (HI) technique for multi-chip assembly. The Metal Embedded Chip Assembly (MECA) process was used on a single thermal test chip to assess the thermal benefits of the embedded copper heat sink. Measurements were taken from the diodes on the thermal test chip as well as from the thermal images recorded with infrared camera. Simulation was done using COMSOL and are in unison agreement with the experimental results.

12.4 Final.2025

Abstract
Etch Pit Density (EPD) is a critical metric for assessing the quality of semiconductor wafers, providing insights into the density of dislocations and other crystal defects. The definition and measurement of robust and significant EPD evaluation parameters are essential for ensuring the performance, stability and cost efficiency of device manufacturing. In recent years the frontiers of low dislocation densities in VB/VGF grown GaAs and InP crystals have been pushed continuously. Traditional methods for EPD evaluation and assessment, while foundational, often fall short in addressing the complexities of modern semiconductor requirements. This paper will highlight the necessity of improving EPD counting and evaluation methods to meet the rigorous demands of contemporary semiconductor applications.

12.17 Final.2025

Abstract
For high-performance GaN-based transistors, minimizing contact resistance is essential to reduce power losses and enhance switching efficiency. Achieving highly- doped contact areas in GaN is challenging due to its high binding energy and self-compensation effects. This study investigates the electrical activation of silicon-implanted GaN-on-sapphire structures using rapid thermal annealing (RTA) and optimized cap layers. Various cap materials, including sputtered and PECVD SiNx, Al2O3, and bilayer approaches, were evaluated for their ability to prevent GaN decomposition during high-temperature annealing. The best-performing cap consisted of a 10 nm thick CVD SiNx layer followed by 10 nm ALD Al2O3 layer, providing effective surface protection up to 1300 °C. Sheet resistance measurements indicate that higher annealing temperatures and optimized spike annealing conditions improve dopant activation, with the lowest sheet resistance of 188 Ω/□ achieved at 1400 °C using a two-spike process. These findings provide insights into optimizing thermal processes for high-performance GaN device fabrication.

3A.2 Final.2025

Abstract
Normally-off high-electron-mobility transistors with p-type NiO gate on an N-polar GaN/AlN material platform are demonstrated. A direct comparison with p-NiO gated HEMTs, Metal-Oxide-Semiconductor (MOS)-gated HEMTs and AlN trench MOSFET devices on the same wafer shows the utility of the NiO in shifting the threshold voltage to positive values. HEMTs with a p-NiO gate exhibit a positive threshold voltage of 1.24 V with a high ON/OFF drain current ratio of 107, a yield as high as 70% is achieved. Breakdown voltages of over 3000 V in co-fabricated AlN trench structures highlight the strong potential of the N-polar GaN/AlN platform for power electronic devices. The potential of this technology for future commercialization/manufacturing is demonstrated.

7A.3 Final.2025

Abstract
With a wide bandgap of 5.4 eV, α-Ga2O3 is a promising material for high-breakdown power devices and solar-blind photodetectors but is difficult to grow due its metastability. Sapphire, being isostructural to α-Ga2O3, is therefore the substrate of choice to stabilise epitaxial layers of α-Ga2O3. Since each sapphire plane imposes different surface energy and strain conditions on the epitaxial layer, the choice of substrate orientation is critical to the stabilisation of α-phase. In this work, Ga2O3 thin films were deposited simultaneously on (11-20), a-plane, (10-10) m-plane, (0001) c-plane, and (01-12) r-plane sapphire substrates using metal-organic chemical vapour deposition (MOCVD), and XRD analysis was performed to confirm the resultant phase of Ga2O3 on each plane. We found that, under the same conditions, Ga2O3 assumed β phase on c-plane, mixed phase α & β on a-plane and r-plane, and pure α phase on m-plane. These results indicate that m-plane is most conducive to growing phase-pure α-Ga2O3 layers via MOCVD, and could open opportunities for future device manufacturing.

8A.2 Final.2025

Abstract
This work presents β-Ga2O3 trench Schottky barrier diodes (TSBDs) with double drift layer structures, achieving a 34% lower on-resistance compared to conventional single drift layer structures, without compromising the off-state performance. The TSBDs exhibit a breakdown voltage of ~2.4 kV, after which the devices were observed to crack along the [010] crystallographic direction in β-Ga2O3. The mechanisms behind breakdown-induced cracking were investigated including using nanoindentation, which revealed that the cracking is due to relatively weak chemical bonding along the [010] direction.

8A.3 Final.2025

Abstract
This study reports the melt growth of β-Ga2O3 single crystals using the Optical Floating Zone (OFZ) technique, and defect analysis in these wafers. X-ray diffraction (XRD) rocking curves show a full width at half maximum (FWHM) of 230 arcsec and the chemical mechanical polished surfaces exhibit a low surface roughness of 1.1 nm. Schottky barrier diodes (SBDs) were fabricated on these substrates and deep-level transient spectroscopy (DLTS) measurements were performed to investigate defects within the bandgap. DLTS analysis revealed a dominant single deep-level trap at 0.69 eV below the conduction band, attributed to Fe impurities from the source material used for melt-growth.

8A.4 Final.2025

Abstract
In this work, Gallium Oxide (β-Ga2O3) based trench Schottky barrier diodes (TSBDs) with field plate edge-termination are reported. The SiNx field plate edge-terminated TSBDs show an improvement in breakdown voltage up to 2.3 kV as compared to the unterminated structures of 1 kV. The electric field simulations show a reduction in peak electric field at the edge of the diodes when terminated with SiNx field plates. Reliability measurements were performed by reverse-bias step-stressing and observing the on-state performance post stressing. An increase in on-resistance for TSBDs with field plate edge termination up to 12% is observed when devices are stressed at 1 kV.

7A.1 Final.2025

Abstract
In this work, we present the first demonstration of InP HBTs grown and fabricated on an engineered InPOSi substrate. Physical and electrical characterizations were performed to measure its crystal quality and device performance. We show that the performance of devices fabricated on an InPOSi substrate is close to devices fabricated on a native InP substrates making such a technology suitable for advanced RF applications. Fabricated devices show ft/fmax of ~140 GHz/70GHz with BVceo/BVcbo of 3.5 V/5.5 V at an ON current density of 8mA/μm2.

3A.5 Final.2025

Abstract
Lateral p-GaN gate-based power HEMTs are fabricated using a 9 μm thick GaN buffer on 200 mm GaN-on-QST® engineered substrates with a poly-AlN core, targeting 1200 V applications. The fabricated devices on engineered p-GaN gate on 9 μm thick GaN buffer show good ON/OFF state electrical characteristics and breakdown ~ 1800 V. The reliability of the fabricated p-GaN HEMTs were evaluated by a 1000-hour high temperature reverse bias (HTRB) stress test at 1200 V. No impact of HTRB stress was observed on electrical parameters and the devices yield a high pass rate.

7A.1 Final.2025

Abstract
In this work, we present the first demonstration of InP HBTs grown and fabricated on an engineered InPOSi substrate. Physical and electrical characterizations were performed to measure its crystal quality and device performance. We show that the performance of devices fabricated on an InPOSi substrate is close to devices fabricated on a native InP substrates making such a technology suitable for advanced RF applications. Fabricated devices show ft/fmax of ~140 GHz/70GHz with BVceo/BVcbo of 3.5 V/5.5 V at an ON current density of 8mA/μm2.

10A.2 Final.2025

Abstract
AlGaN-based deep-ultraviolet (DUV) laser diodes (LDs) are expected to be applied to various applications such as sterilization, sensing, and laser processing as compact, efficient, and eco-friendly deep-ultraviolet light sources. To realize laser diodes operating in the DUV wavelength range (200 nm to 280 nm), our research group has achieved major breakthroughs such as high-quality AlGaN thin film crystals grown on AlN single-crystal substrates and p-type conductivity control through distributed polarization doping. As a result, pulsed lasing at room temperature was demonstrated. Furthermore, continuous-wave (CW) lasing has been successfully achieved by suppressing dislocation formation through stress concentration suppression and further design improvements. In this presentation, we will review the research results of our group on DUV LD devices and describe the key technologies that played an important role in these achievements.

10B.2 Final.2025

Abstract
This study presents a novel approach to device yield estimation based on the non-contact, corona-based QUAD(Quality, Uniformity, and Defects) technique for inline defect mapping in SiC epitaxial layers. The approach is applied to a merged PiN Schottky diode manufacturing process and is compared to final wafer level electrical data. A new analysis method for QUAD defect mapping is introduced, incorporating die yield bin maps based on indie depletion voltage values, allowing for a direct comparison with final electrical device performance. Micro-scale, QUAD and voltage data within each individual diode can gain further insight into the electrical nature of the defects causing the device failure. The results demonstrate a strong correlation between the inline QUAD bin map results and final device electrical properties, highlighting the potential of QUAD as a practical and powerful inline tool. This technique offers a complementary approach to UVPL defect imaging, identifying electrically active defects and enhancing estimations of the final production yield.

11A.2 Final.2025

Abstract
Coherent pluggable optics at 800 Gb/s and beyond are set to play a dominant role in optical networks over the next decade.
Infinera’s pluggable solutions are based on a monolithically integrated InP-based photonic integrated circuit (PIC), combining devices and functions required for a coherent optical transceiver. We will discuss the architecture and performance of several generations of InP-based PICs. Increased complexity in chip functionality has resulted in a need for increased fabrication complexity from III-V epitaxy, through wafer fab, die fab, and test. Through continuous learning and improvement, Infinera has fine-tuned the essential elements to successfully manufacture high-performance InP-based PICs. We will discuss manufacturing capability along with relevant yield and production metrics highlighting the manufacturability and scalability of this platform for pluggable components.
Recent industry trends have opened new and exciting markets where InP PICs offer benefits unmatched by any other technology. To meet these even higher volume manufacturing demands Infinera is investing in improved process technology and higher production capacity. We will discuss key challenges associated with this transition, and the outlook for further adoption of PIC technology.

12.2 Final.2025

Abstract
RF-plasma assisted nitridation was used to transform (100) -Ga2O3 to (0001) wurtzite GaN and subsequently grow a 520 nm p-GaN cap layer over 5 intervals. The final step involved a 11.5 hour anneal at the growth temperature of 680 C to allow for equilibration inside the crystal body. The nitridated film was characterized via X-ray diffraction (XRD), which revealed peaks distinct from the (0001) family. Analysis of these distinct peaks revealed varying (𝒉𝟎𝒍) orientations. We theorize that the alternate orientations are forming to accommodate the growing GaN film, gradually shifting towards the ideal heteroepitaxy plane of (𝟐̅𝟎𝟏). XRD rocking curves of the (0002) GaN were used to analyze crystallinity as a function of thickness. Results showed a transformation at the 120 nm interval, from a single Gaussian-like peak to a broad-narrow dual peak configuration. The FWHM’s were extracted and plotted against a previous study, indicating narrower, improved peak of 20%.

12.3 Final.2025

Abstract
Silicon nitride shadowed selective area growth (SNS-SAG) for homoepitaxy of GaN via RF plasma-assisted molecular beam epitaxy (PAMBE) has been shown to avoid the defects that arise from conventional selective area processing methods such as inductively coupled plasma reactive ion etching (ICP-RIE) and ion implantation. This work investigates the extension of this method to improve the heteroepitaxy of GaN on β-Ga2O3 by modifying the makeup of the SNS-SAG mask. Gallium rich and nitrogen rich GaN films are grown with SNS-SAG masks on β-Ga2O3 substrates. While current device performance has yet to be optimized, the adapted SNS-SAG mask retains both function and structural integrity as shown by scanning electron microscopy (SEM).

12.6 Final.2025

This paper presents Indium Tin Oxide (ITO) films developed using a pulsed DC off-axis sputtering chamber on 300mm substrates to obtain transparent-ohmic contact for pGaN. Film optoelectrical and microstructure properties were investigated per comparison for different deposition techniques such as single ITO target, alloy by co-deposition from two targets (In2O3 and SnO2) and for stacks including different interfacial layers, such as In-rich ITO and Ni. A ranking of the specific contact resistivity of all the films was determined after integration on Transmission Line Method (TLM) devices. A correlation of the specific contact resistivity with film first layer’s texture dependent on film process, thickness and material was observed.

7A.4 Final.2025

Abstract
The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Recently proton implantation has revealed its capability to block stacking fault expansion. We have evidenced through material characterization and electrical measurements of 1200 V PIN diodes that bipolar degradation can be mitigated above 1000 A/cm². A strong robustness has been evidenced through UV induced stacking faults. Electrical results are showing no visible bipolar degradation after a 600sec-2250 A/cm² stress test, while the reference material is showing a ~500mV drift at the device rated current of 10A.

6B.3 Final.2025

Abstract
Polar Light Technologies has developed an innovative microLED solution that generates RGB emission within a single material system, achieving a significant leap in microLED technology, especially for micro-projector and display applications. By employing a unique bottom-up approach based on hexagonal GaN pyramids with InGaN quantum wells (QW), microLEDs with dominant emission at 470 nm, 520 nm and 625 nm were demonstrated without the need for separate phosphor or quantum dot color conversion. This integration will not only simplify the future manufacturing process but also enhances the color uniformity and stability throughout a device.

12.10 Final.2025

Abstract
At ATL, innovation drives the development of new technologies to meet customer needs, including in the semiconductor fabrication process. Shifts in processing can lead to issues like cross-contamination, impacting processes such as L-Band power transistor production. Residue left after photoresist strip processes caused concerns, affecting wafer quality and potentially leading to emitter-base shorts. Through a rigorous investigation and experimentation with different photoresist strip methods, a more effective approach using an alternate Asher tool was found. Implementing this new method significantly reduced residue, improving production yield and resolving process challenges in semiconductor manufacturing at ATL.

12.18 Final.2025

Abstract
This material presents the technology development on 0.25um GaN High Electron Mobility Transistor (HEMT) on Silicon in WAVETEK Microelectronics. Epitaxy, process, BVD and RF characteristics are included in this material. The first process flow is designed for averaged power ≤ 20W and operation voltage@28V diverse power amplifier (PA) applications, e.g. massive MIMO basestation PA or phase array radar. DC performance of 4x100um device showed breakdown voltage > 200V. And RF results show fT, fmax (Vd=28V) = 28, 95 GHz, respectively. MSG/MAG= 23 dB @Vd= 28V and frequency= 3.5GHz. With optimized epitaxy structure and process, current collapse has been improved to 11.3%. Based on continuous wave (CW) load-pull measurement with harmonic tuning, (Vd=28V, Jc=20mA/mm, @3.5GHz), PAE@P3dB can achieve 70%, Gain= 19dB and Pout@P3dB can reach 32 dBm. For the other application of Vd=10V, e.g. WiFi Router PA and direct to cell PA, the 0.4mm HEMT device can achieve 2.1W. Adjacent Channel Leakage Ratio (ACLR) has been measured. The 4x100um HEMT results of raw ACPR (without DPD) are -39.3dBc/-38.6dBc. The overall performance is promising for 0.25um GaN on Silicon technology. The overall performance is promising for 0.25um GaN on Silicon technology.

11B.2 Final.2025

Abstract
Design of experiments (DOE) were performed to optimize resistance uniformity for TaN thin film resistors (TFR) across the Ta target’s life cycle. Fine-tuned photo-lithography recipes with exposure dose compensation (DC) minimized resistance variation introduced during the resistor layer’s (RL) photolithography and deposition processes. Experimental studies revealed how critical dimensions (CD) are influenced by the photoresist’s chemical amplification, substrate’s thermal history during post-exposure bake (PEB), and the coupling time (CT) between process-sensitive steps. The implementation of additional process controls within the RL fabrication process enhanced process capability (Cpk), tightened statistical process control (SPC) of TaN-related electrical parameters, and improved probe yield.

10B.3 Final.2025

Abstract
Silicon Carbide (SiC) power MOSFET performance depends on many key process and material properties. The drift layer active carrier concentration and thickness are important factors for defining device properties. Drift layer carrier concentration can be monitored easily by capacitance-voltage (CV) measurements. The leakage current (Ileak), breakdown voltage (VBD) and on-state resistivity (RON-sp) are all highly affected by control of the active carrier concentration profile and are monitorable by current-voltage (IV) measurements. Inadequate quality of the 4H-SiC epitaxial processes can degrade device performance and induce failure of the power MOSFET. In this paper, a high repeatability mercury probe is used to monitor these crucial electrical parameters and allows for a rapid response in improving and predicting final device behavior.

7A.4 Final.2025

Abstract
The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Recently proton implantation has revealed its capability to block stacking fault expansion. We have evidenced through material characterization and electrical measurements of 1200 V PIN diodes that bipolar degradation can be mitigated above 1000 A/cm². A strong robustness has been evidenced through UV induced stacking faults. Electrical results are showing no visible bipolar degradation after a 600sec-2250 A/cm² stress test, while the reference material is showing a ~500mV drift at the device rated current of 10A.

2A.3 Final.2025

Abstract
We present the performances of our GaN MISHEMTs, using a thin buffer grown on SiC substrate, to pave the way for lateral GaN devices to exploit power applications in the voltage range up to 1700 V. Uni- and bi-directional MISHEMTs based on gate and source-connected field plate, with LGD = 21 μm achieve a breakdown voltage over 1800 V at a drain-source and gate currents less than 50 nA/mm. The on-resistance of the 1 mm gate width uni- and bidirectional devices were 9.5 Ω∙mm and 13.5 Ω∙mm, respectively, with a specific on-resistance of 2.7 mΩ∙cm2 and 4.4 mΩ∙cm2, respectively. The 1mm single MISHEMT results in a high Baliga figure of merit (BFOM) of 1.2 GW/cm2. A 147 mm gate width MISHEMT delivered 20 A pulse IDS current, at VGS =0 V and VDS = 1.5 V. Moreover, the MISHEMTs feature encouraging and superior stand in the breakdown voltage vs. on-resistance benchmark to commercial devices. We addressed the potential of the GaN-HEMTs to cover

12.19 Final.2025

Abstract
ITO layers were sputter-deposited onto commercially available vertical p/p+ diamond structures consisting of 5 μm thick p-type (1.2 × 1016 cm-3) drift layers deposited by Chemical Vapor Deposition on 250 μm thick heavily B-doped (3 × 1020 cm-3) single crystal substrates. The ITO is found to form a type II band alignment allowing Ohmic contact to the p-type diamond and creating a vertical n-p heterojunction. The maximum reverse breakdown of heterojunction rectifiers was ~1.1 kV, with an on-resistance (RON) of 13 mΩ•cm2, leading to a power figure-of-merit of 99.3 MW/cm2. The on-voltage was 1.4 V, diode ideality factor 1.22, with a reverse recovery time of 9.5 ns for 100 μm diameter rectifiers. The on/off ratios when switching from -5 V forward to 100 V reverse were in the range of 1011 to 1012. This is a simple approach to realizing high performance vertical diamond-based rectifiers for power switching applications.

4B.2 Final.2025

Abstract
This paper discusses Qorvo’s recent release of Cu Pillar (CuP) interconnect technology with Ni barrier on high frequency Gallium Nitride (GaN) HEMTs fabricated on Silicon Carbide (SiC) 150 mm substrates. Ongoing multi-temperature High Temperature Storage (HTS) tests indicate > 2×106 h median lifetime for CuP joints at 85ºC. Different types of CuP Ni plating are being studied which display a difference in lifetimes. Results demonstrate the use of ENEPIG finish on the laminate substrates could further increase CuP solder-joint reliability, allowing their use at temperatures up to 125ºC.

4A.4 Final.2025

Abstract
E-mode p-GaN -gate RF HEMT with engineered Mg doping profile was developed and demonstrated for high power amplifier application. Through the design of a low-temperature MOCVD Mg doping profile and a reduction in Mg doping concentration, the diffusion of Mg into AlGaN is minimized compared to traditionally high Mg-doping grown p-GaN. This design enhances the gate modulation capability of p-GaN for RF applications, resulting in a higher gm peak. In addition, the Poole–Frenkel (PF) tunneling induced flicker noise was also suppressed at high input power swing due to low inactivated Mg induced traps. With the engineered Mg-doping profile design, a 61.4 % PAE was achieved together with an output power density close to 1 W/mm at VDS of 10 V which exhibit a highly potential for satellite direct-to-cell and FR3 mobile phone single voltage supply PA applications.

12.18 Final.2025

Abstract
This material presents the technology development on 0.25um GaN High Electron Mobility Transistor (HEMT) on Silicon in WAVETEK Microelectronics. Epitaxy, process, BVD and RF characteristics are included in this material. The first process flow is designed for averaged power ≤ 20W and operation voltage@28V diverse power amplifier (PA) applications, e.g. massive MIMO basestation PA or phase array radar. DC performance of 4x100um device showed breakdown voltage > 200V. And RF results show fT, fmax (Vd=28V) = 28, 95 GHz, respectively. MSG/MAG= 23 dB @Vd= 28V and frequency= 3.5GHz. With optimized epitaxy structure and process, current collapse has been improved to 11.3%. Based on continuous wave (CW) load-pull measurement with harmonic tuning, (Vd=28V, Jc=20mA/mm, @3.5GHz), PAE@P3dB can achieve 70%, Gain= 19dB and Pout@P3dB can reach 32 dBm. For the other application of Vd=10V, e.g. WiFi Router PA and direct to cell PA, the 0.4mm HEMT device can achieve 2.1W. Adjacent Channel Leakage Ratio (ACLR) has been measured. The 4x100um HEMT results of raw ACPR (without DPD) are -39.3dBc/-38.6dBc. The overall performance is promising for 0.25um GaN on Silicon technology. The overall performance is promising for 0.25um GaN on Silicon technology.

4A.4 Final.2025

Abstract
E-mode p-GaN -gate RF HEMT with engineered Mg doping profile was developed and demonstrated for high power amplifier application. Through the design of a low-temperature MOCVD Mg doping profile and a reduction in Mg doping concentration, the diffusion of Mg into AlGaN is minimized compared to traditionally high Mg-doping grown p-GaN. This design enhances the gate modulation capability of p-GaN for RF applications, resulting in a higher gm peak. In addition, the Poole–Frenkel (PF) tunneling induced flicker noise was also suppressed at high input power swing due to low inactivated Mg induced traps. With the engineered Mg-doping profile design, a 61.4 % PAE was achieved together with an output power density close to 1 W/mm at VDS of 10 V which exhibit a highly potential for satellite direct-to-cell and FR3 mobile phone single voltage supply PA applications.

12.18 Final.2025

Abstract
This material presents the technology development on 0.25um GaN High Electron Mobility Transistor (HEMT) on Silicon in WAVETEK Microelectronics. Epitaxy, process, BVD and RF characteristics are included in this material. The first process flow is designed for averaged power ≤ 20W and operation voltage@28V diverse power amplifier (PA) applications, e.g. massive MIMO basestation PA or phase array radar. DC performance of 4x100um device showed breakdown voltage > 200V. And RF results show fT, fmax (Vd=28V) = 28, 95 GHz, respectively. MSG/MAG= 23 dB @Vd= 28V and frequency= 3.5GHz. With optimized epitaxy structure and process, current collapse has been improved to 11.3%. Based on continuous wave (CW) load-pull measurement with harmonic tuning, (Vd=28V, Jc=20mA/mm, @3.5GHz), PAE@P3dB can achieve 70%, Gain= 19dB and Pout@P3dB can reach 32 dBm. For the other application of Vd=10V, e.g. WiFi Router PA and direct to cell PA, the 0.4mm HEMT device can achieve 2.1W. Adjacent Channel Leakage Ratio (ACLR) has been measured. The 4x100um HEMT results of raw ACPR (without DPD) are -39.3dBc/-38.6dBc. The overall performance is promising for 0.25um GaN on Silicon technology. The overall performance is promising for 0.25um GaN on Silicon technology.

12.11 Final.2025

Abstract
In this paper, we focus on a simple hardware reconfiguration of CMP tools by deploying a slurry injection system (SIS) that modifies the slurry flow distribution, resulting in a more uniformly distributed thin layer of slurry on the polishing pad. The benefits of deploying the SIS on the CMP tools are clearly demonstrated: a 40-50% reduction in slurry flow rate — resulting in increasing throughput due to higher removal rate. A 2- 4% improvement in planarization was also obtained on patterned wafers polished with 5 kÅ of silicon dioxide (SiO2) deposited on top of a titanium/aluminum (Ti/Al) metal stack on a silicon substrate.

6B.4 Final.2025

ABSTRACT
In this work, we report the development of a high-precision fabrication process for microcavity VCSELs operating at cryogenic temperatures with oxide-aperture sizes below 3 μm. To address the critical challenge of controlling oxide-aperture size during wet oxidation, a novel hybrid etch mask combining SiNx and PR was introduced, enabling vertical mesa sidewall profiles with improved reliability and process uniformity. This approach enhances the accuracy of oxide formation, crucial for scaling down VCSEL apertures while maintaining thermal and optical performance. The fabricated Cryo-VCSEL with 1.7 m aperture demonstrates exceptional output power of 3.93 mW and modulation bandwidth exceeding 50 GHz at 2.9 K, with successful PAM-4 data transmission at 112 Gbps. The process yields minimal aperture variation (~ 0.5 μm IQR) across samples, ensuring suitability for parameter extraction and VCSEL array integration. These advancements establish a scalable fabrication platform for high-speed, cryogenic VCSELs, supporting future optical interconnects in quantum computing systems.

6A.3 Final.2025

Abstract
This paper presents Circuits Integrated Hellas’s (CIH) innovative use of III-V compound semiconductors with advanced 3D packaging. CIH introduces disruptive, high-performance solutions for satellite communication (SatCom) applications, leveraging System-in-Package (SiP) and Antenna-in-Package (AiP) methodologies. These approaches minimize the weight, volume, and cost of flat-panel phased array antennas, addressing a critical need in modern space communications

12.13 Final.2025

Abstract
Dislocation of GaN epi has a strong correlation with reliability and electronic property of a GaN pHemt device. From technology development and field experience, dislocation under a device could cause possible reliability failure especially HTRB. In failure analysis for GaN dislocation, two beam condition of TEM is a common method, but the limitation of sample dimension and high cost are its disadvantages. In the literature, top-view observation by OM/SEM for etched epi by acid/base could be a reliable method for dislocation identification and density calculation[1][2][3]. By a series of experiments, we have developed an etching method by using molten KOH to obtain top-view SEM images of etched GaN epi and their correlation between defect density and reliability/electrical performance.

2B.3 Final.2025

Abstract
This report investigates 940 nm vertical-cavity surface-emitting lasers (VCSELs) with three junctions (3J). The study focuses on the impact of oxide layers on the electrical and optical performance of these devices under various pulse conditions. Heat accumulation is a significant challenge in VCSELs, and shorter pulse durations reduce heat generation, improving thermal performance and minimizing lateral carrier diffusion in multi-junction structures. The results indicate that incorporating multiple oxide layers enhances carrier confinement, enabling output power exceeding 120 watts with 1.6-nanosecond pulses. However, using a single oxide layer decreases resistance and improves thermal dissipation, while maintaining output power above 100 watts. Spectral measurements revealed a red shift of less than 0.8 nm, corresponding to temperature variations of less than 12°C at 40A current injection. These findings provide valuable insights into the benefits and limitations of multi-junction VCSELs for next-generation sensing applications.

2B.4 Final.2025

Abstract
We present a monolithic dual-wavelength DFB laser designed for terahertz applications. This laser achieves an optical power of up to 144.41 mW with a low threshold current of 16.2 mA. The power difference between the two primary modes is maintained within 1 dB, while each mode exhibits a side-mode suppression ratio exceeding 35 dB, ensuring stable dual-wavelength operation. Additionally, the laser exhibits a low-frequency noise floor of 2.81 × 10⁻⁴ and 2.15 × 10⁴ Hz²/Hz for the longer and shorter wavelengths, respectively. These results underscore the potential of the dual-wavelength DFB laser as a compact and efficient solution for terahertz systems.