Abstract
This study presents a novel approach to device yield estimation based on the non-contact, corona-based QUAD(Quality, Uniformity, and Defects) technique for inline defect mapping in SiC epitaxial layers. The approach is applied to a merged PiN Schottky diode manufacturing process and is compared to final wafer level electrical data. A new analysis method for QUAD defect mapping is introduced, incorporating die yield bin maps based on indie depletion voltage values, allowing for a direct comparison with final electrical device performance. Micro-scale, QUAD and voltage data within each individual diode can gain further insight into the electrical nature of the defects causing the device failure. The results demonstrate a strong correlation between the inline QUAD bin map results and final device electrical properties, highlighting the potential of QUAD as a practical and powerful inline tool. This technique offers a complementary approach to UVPL defect imaging, identifying electrically active defects and enhancing estimations of the final production yield.
