3A.2 - Normally-Off N-Polar GaN/AlN Transistors with p-NiO Gate Stacks - CS MANTECH Conference CS MANTECH Conference CS MANTECH Conference

3A.2 – Normally-Off N-Polar GaN/AlN Transistors with p-NiO Gate Stacks

C. Zhang, University of Bristol

Y. Yin, University of Bristol

I. Furuhashi, Nagoya University

M. Pristovsek, Nagoya University

M. Kuball, University of Bristol, Bristol, UK

Matthew Smith, University of Bristol

3A.2 Final.2025

Abstract
Normally-off high-electron-mobility transistors with p-type NiO gate on an N-polar GaN/AlN material platform are demonstrated. A direct comparison with p-NiO gated HEMTs, Metal-Oxide-Semiconductor (MOS)-gated HEMTs and AlN trench MOSFET devices on the same wafer shows the utility of the NiO in shifting the threshold voltage to positive values. HEMTs with a p-NiO gate exhibit a positive threshold voltage of 1.24 V with a high ON/OFF drain current ratio of 107, a yield as high as 70% is achieved. Breakdown voltages of over 3000 V in co-fabricated AlN trench structures highlight the strong potential of the N-polar GaN/AlN platform for power electronic devices. The potential of this technology for future commercialization/manufacturing is demonstrated.